Patent application number | Description | Published |
20120011090 | METHODS AND SYSTEMS FOR THREE-MEMRISTOR SYNAPSE WITH STDP AND DOPAMINE SIGNALING - The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling. | 01-12-2012 |
20120011092 | METHODS AND SYSTEMS FOR MEMRISTOR-BASED NEURON CIRCUITS - Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced. | 01-12-2012 |
20120036099 | METHODS AND SYSTEMS FOR REWARD-MODULATED SPIKE-TIMING-DEPENDENT-PLASTICITY - Certain embodiments of the present disclosure support techniques for simplified hardware implementation of the reward-modulated spike-timing-dependent plasticity (STDP) learning rule in networks of spiking neurons. | 02-09-2012 |
20140043962 | STATISTICS AND FAILURE DETECTION IN A NETWORK ON A CHIP (NoC) NETWORK - Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC. | 02-13-2014 |
20140046885 | METHOD AND APPARATUS FOR OPTIMIZED REPRESENTATION OF VARIABLES IN NEURAL SYSTEMS - Certain aspects of the present disclosure support a technique for optimized representation of variables in neural systems. Bit-allocation for neural signals and parameters in a neural network described in the present disclosure may comprise allocating quantization levels to the neural signals based on at least one measure of sensitivity of a pre-determined performance metric to quantization errors in the neural signals, and allocating bits to the parameters based on the at least one measure of sensitivity of the pre-determined performance metric to quantization errors in the parameters. | 02-13-2014 |
20140101661 | METHOD AND APPARATUS FOR TIME MANAGEMENT AND SCHEDULING FOR SYCHRONOUS PROCESSING ON A CLUSTER OF PROCESSING NODES - Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not. | 04-10-2014 |
20140252531 | SYSTEMS AND METHODS FOR HARVESTING DISSIPATED HEAT FROM INTEGRATED CIRCUITS (ICS) IN ELECTRONIC DEVICES INTO ELECTRICAL ENERGY FOR PROVIDING POWER FOR THE ELECTRONIC DEVICES - Systems and methods for harvesting dissipated heat from integrated circuits (ICs) in electronic devices into electrical energy for providing power for the electronic devices are disclosed. In one embodiment, energy transferred from one or more ICs in the form of dissipated heat is harvested to convert at least a portion of this dissipated heat into electricity. This power can be used to provide power to the ICs to reduce overall power consumption by the electronic device. The harvested dissipated heat can be supplied to ICs in the electronic device to provide power to the ICs. Alternatively, or in addition, the harvested dissipated heat can be stored in an energy storage device to provide power to the ICs at a later time. | 09-11-2014 |
20140351190 | EFFICIENT HARDWARE IMPLEMENTATION OF SPIKING NETWORKS - Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. | 11-27-2014 |
20140365413 | EFFICIENT IMPLEMENTATION OF NEURAL POPULATION DIVERSITY IN NEURAL SYSTEM - Certain aspects of the present disclosure support a technique for efficient implementation of neural population diversity in neural systems. A set of parameters for each class of artificial neurons of a plurality of classes can be stored in a storage medium. A generator can be configured to obtain noise parameters for each class of artificial neurons in the neural system. After that, the noise parameters can be combined with the set of parameters for each class of artificial neurons to obtain a dithered set of parameters for each class of artificial neurons. The dithered set of parameters can be stored for each class of artificial neurons to be used for a neuron model for the artificial neurons that emulates behavior of the artificial neurons in the neural system. | 12-11-2014 |
20150046381 | IMPLEMENTING DELAYS BETWEEN NEURONS IN AN ARTIFICIAL NERVOUS SYSTEM - Methods and apparatus are provided for implementing delays in an artificial nervous system. Synaptic and/or axonal delays between a post-synaptic artificial neuron and one or more pre-synaptic artificial neurons may be accounted for at the post-synaptic artificial neuron. One example method for managing delay between neurons in an artificial nervous system generally includes receiving, at a post-synaptic artificial neuron, input current values from one or more pre-synaptic artificial neurons; accounting for delays between the one or more pre-synaptic artificial neurons and the post-synaptic artificial neuron at the post-synaptic artificial neuron; and determining a state of the post-synaptic artificial neuron based at least in part on at least a portion of the input current values, according to the accounting. | 02-12-2015 |
20150046382 | COMPUTED SYNAPSES FOR NEUROMORPHIC SYSTEMS - Methods and apparatus are provided for determining synapses in an artificial nervous system based on connectivity patterns. One example method generally includes determining, for an artificial neuron, an event has occurred; based on the event, determining one or more synapses with other artificial neurons based on a connectivity pattern associated with the artificial neuron; and applying a spike from the artificial neuron to the other artificial neurons based on the determined synapses. In this manner, the connectivity patterns (or parameters for determining such patterns) for particular neuron types, rather than the connectivity itself, may be stored. Using the stored information, synapses may be computed on the fly, thereby reducing memory consumption and increasing memory bandwidth. This also saves time during artificial nervous system updates. | 02-12-2015 |
20150066826 | METHODS AND APPARATUS FOR IMPLEMENTING A BREAKPOINT DETERMINATION UNIT IN AN ARTIFICIAL NERVOUS SYSTEM - Methods and apparatus are provided for using a breakpoint determination unit to examine an artificial nervous system. One example method generally includes operating at least a portion of the artificial nervous system; using the breakpoint determination unit to detect that a condition exists based at least in part on monitoring one or more components in the artificial nervous system; and at least one of suspending, examining, modifying, or flagging the operation of the at least the portion of the artificial nervous system, based at least in part on the detection. | 03-05-2015 |