Vatter
Forrest C. Vatter, Bedford, NH US
Patent application number | Description | Published |
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20140222397 | FRONT-END SIGNAL GENERATOR FOR HARDWARE IN-THE-LOOP SIMULATION - A front-end signal generator for hardware-in-the-loop simulators of a simulated missile is disclosed. The front-end signal generator is driven by the Digital Scene And Reticle Simulation-Hardware In The Loop (DSARS-HITL) simulator. The simulator utilizes a computer to calculate irradiance on an Electro-Optical/Infrared (EO/IR) detector. The generator converts irradiance values into voltages that are injected into the missile's electronics during simulation. The conversion is done with low latency and a high dynamic range sufficient for hardware-in-the-loop simulation. The generator is capable of emulating laser pulse inputs that would be present during laser-based jammer countermeasures. Computer control of the generator occurs via front-panel-data-port (FPDP). | 08-07-2014 |
Holger Vatter, Buettelborn DE
Patent application number | Description | Published |
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20090245493 | System and Method for Displaying Call Flows and Call Statistics - The system and method identify a plurality of call flow events in a call analysis system. Call statistics are associated with the call flow events. The call flow events are organized into event groups each containing a plurality of call flow events. Once an event group is selected, call statistics for the events of the event group are displayed. In addition, the system and method allow for selection of individual call flow events in order to display calls associated with the events. | 10-01-2009 |
Robert F. Vatter, St. Albans, VT US
Patent application number | Description | Published |
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20160049492 | VERTICAL P-TYPE, N-TYPE, P-TYPE (PNP) JUNCTION INTEGRATED CIRCUIT (IC) STRUCTURE, AND METHODS OF FORMING - Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction. | 02-18-2016 |
20160049501 | Method to build vertical PNP in a BICMOS technology with improved speed - Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region. | 02-18-2016 |
Thomas E. Vatter, Holyoke, MA US
Patent application number | Description | Published |
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20140318088 | PARTICLE SEPARATOR - A particle separator comprises a vessel, a fluid inlet, a fluid swirl passage, a scupper cavity, a first fluid outlet, and a second fluid outlet. The vessel includes a vessel sidewall extending between a vessel top side and a vessel bottom side. The fluid swirl passage includes a first passage end in communication with a fluid inlet disposed on the vessel top side. A second passage end is in communication with a vessel swirl cavity defined at least in part by an inner surface of the vessel sidewall. The scupper cavity includes a scupper entrance disposed along the inner surface of the vessel sidewall, and is spaced circumferentially apart from the second passage end. The first fluid outlet is in communication with the scupper cavity and disposed on the vessel bottom side. The second fluid outlet is disposed above the first fluid outlet in communication with the vessel swirl cavity. | 10-30-2014 |