Van Schaijk, Eindhoven
Rob Van Schaijk, Eindhoven NL
Patent application number | Description | Published |
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20110074247 | Systems and Methods for Resonance Frequency Tuning of Micromachined Structures - A microstructure according to embodiments of the present invention comprises a substrate, and a resonant structure having a resonance frequency and comprising a seismic mass and suspension elements for suspending the seismic mass at two opposite sides onto the substrate. The substrate is adapted for functioning as a tuning actuator adapted for applying stress onto the suspension elements, thus changing the stiffness of the suspension elements. This way, the resonance frequency of the microstructure may be adapted to input vibration frequencies which may vary over time or may initially be unknown. By adapting the resonance frequency of the resonant structure, a suitable power may be generated, even in circumstances of variable input frequencies. | 03-31-2011 |
20130076202 | MICRO-ELECTROMECHANICAL GENERATOR AND ELECTRIC APPARATUS USING SAME - Disclosed is a highly reliable inductive vibration power generator wherein mechanical damping caused by the phenomenon of electrostatic pulling-in (stiction) and the like is suppressed even if the potential of an electret is increased and/or the gap between an electrode and the electret is reduced in order to increase the amount of power generation. The two surfaces of a movable substrate are respectively provided with first electrets and second electrets. By means of providing first electrodes and second electrodes to a lower substrate and an upper substrate and facing the respective electrets with a predetermined gap therebetween, electrostatic force is caused to arise on both sides of the movable substrate, and the pulling of the movable substrate in only one direction is prevented. | 03-28-2013 |
Robertus Van Schaijk, Eindhoven NL
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20120255349 | MICRO-POWER SYSTEMS - A micro-power system and a tire pressure monitoring system that includes an energy harvesting module and a computing device are disclosed. In one aspect, the energy harvesting module comprises an energy harvesting unit having a combined vibration energy/RF energy harvester. A single sensing element is used for both vibration energy harvest and for RF communication including RF energy harvesting. Energy harvested is transmitted to power management module which powers components of the energy harvesting module. Data relating to sensor output from the single sensing element is transmitted to a microcontroller and transmitted to a microprocessor unit on the computing device. | 10-11-2012 |
Robertus T.f. Van Schaijk, Eindhoven NL
Patent application number | Description | Published |
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20080272427 | Sonos Memory Device With Reduced Short-Channel Effects - A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer ( | 11-06-2008 |
20090242964 | NON-VOLATILE MEMORY DEVICE - A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces. | 10-01-2009 |
20090268527 | SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE - The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-V | 10-29-2009 |
Robertus T. F. Van Schaijk, Eindhoven NL
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20090298293 | Etching with Improved Control of Critical Feature Dimensions at the Bottom of Thick Layers - The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material. | 12-03-2009 |
20100264498 | MANUFACTURING A MEMS ELEMENT HAVING CANTILEVER AND CAVITY ON A SUBSTRATE - Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode ( | 10-21-2010 |
20110260267 | MEMS DEVICES AND FABRICATION THEREOF - A MEMS device and method, comprising: a substrate; a beam; and a cavity located therebetween; the beam comprising a first beam layer and a second beam layer, the first beam layer being directly adjacent to the cavity, the second beam layer being directly adjacent to the first beam layer; the first beam layer comprising a metal or a metal alloy containing silicon; and the second beam layer comprising a metal or a metal alloy substantially not containing silicon. Preferably the second beam layer is thicker than the first beam layer e.g. at least five times thicker, and the first beam layer comprises a metal or alloy containing between 1% and 2% of silicon. The second beam layer provides desired mechanical and/or optical properties whilst the first beam layer prevents spiking. | 10-27-2011 |
Robertus Theodorus Franciscus Van Schaijk, Eindhoven NL
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20090179254 | Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device - Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the material of at least one of the current-carrying channel region and/or the source and drain regions is in an elastically strained state. | 07-16-2009 |
Robertus Theodorus Fransiscus Van Schaijk, Eindhoven NL
Patent application number | Description | Published |
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20080265306 | Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same - A non-volatile memory device ( | 10-30-2008 |
20100173488 | NON-VOLATILE MEMORY WITH ERASE GATE ON ISOLATION ZONES - The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate ( | 07-08-2010 |