Patent application number | Description | Published |
20080272427 | Sonos Memory Device With Reduced Short-Channel Effects - A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer ( | 11-06-2008 |
20090268527 | SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE - The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-V | 10-29-2009 |
20090278186 | Double Gate Transistor and Method of Manufacturing Same - A double gate transistor on a semiconductor substrate ( | 11-12-2009 |
20100308394 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD - A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed. | 12-09-2010 |
Patent application number | Description | Published |
20080265306 | Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same - A non-volatile memory device ( | 10-30-2008 |
20100117138 | NONVOLATILE MEMORY CELL COMPRISING A NONWIRE AND MANUFACTURING METHOD THEREOF - A memory cell ( | 05-13-2010 |
20100173488 | NON-VOLATILE MEMORY WITH ERASE GATE ON ISOLATION ZONES - The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate ( | 07-08-2010 |
20120060589 | SENSOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A sensor device for analyzing fluidic samples is provided, wherein the sensor device comprises a stacked sensing arrangement comprising at least three sensing layers and a multilayer structure, wherein the multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and wherein the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole. | 03-15-2012 |
20120250401 | PHASE CHANGE MEMORY (PCM) ARCHITECTURE AND A METHOD FOR WRITING INTO PCM ARCHITECTURE - A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described. | 10-04-2012 |
20140167055 | METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT - Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor. | 06-19-2014 |
20140269075 | 2T AND FLASH MEMORY ARRAY - Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described. | 09-18-2014 |