Patent application number | Description | Published |
20100109925 | SIGNAL PROCESSOR WITH ANALOG RESIDUE - In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal. | 05-06-2010 |
20100140452 | Dual Mode Source Follower for Low and High Sensitivity Applications - In certain embodiments, a unit cell is provided. The unit cell may include a high sensitivity path and a low sensitivity path. The high sensitivity path may include a first transistor and a first switch. The first switch may couple an output node to the first transistor. The low sensitivity path may include a capacitor. A second switch may couple the high sensitivity path to the low sensitivity path. A third switch may couple the high sensitivity path and the low sensitivity path to a voltage node. | 06-10-2010 |
20100176275 | Multipurpose Photodetector Amplifier and Control Methods - In certain embodiments, a system is provided for image capture that includes a unit cell that includes a Capacitor TransImpedance Amplifier (CTIA) subcircuit, a Source Follower per Detector (SFD) subcircuit, and a Direct Injection (DI) subcircuit. The unit cell may operate using one of the subcircuits selected in response to a control signal. A column amplifier may be coupled to the unit cell. The column amplifier may be operable to receive an intermediate signal from the unit cell and couple components of the column amplifier corresponding to the selected subcircuit in response to the control signal. The column amplifier may generate an output signal from the intermediate signal using the coupled components of the column amplifier. | 07-15-2010 |
20100177224 | Image Device Having a Plurality of Detectors in a Time Delay and Integration (TDI) Configuration and Associated Method - In certain embodiments, an imaging device includes an image sensor that includes a detector array. The detector array includes a plurality of detectors operable to receive a charge generated by light. The detector array also includes a plurality of detector sub-arrays each including one or more of the plurality of detectors. The one or more detectors of each detector sub-array are in a time delay and integration (TDI) configuration. The image sensor of the imaging device is operable to, for each of the plurality of detector sub-arrays of the detector array, generate an image signal corresponding to a scan of an object. | 07-15-2010 |
20100177229 | Image Sensing System And Method Utilizing A Mosfet - A unit cell includes a MOSFET and an integration capacitor. The MOSFET includes a source, a drain, and a gate. The drain is coupled to the source, and the MOSFET is operable to store a first portion of an electric charge corresponding to a detected light intensity. The integration capacitor includes a first end and a second end. The first end is coupled to the drain of the MOSFET and the second end is coupled to a ground. The integration capacitor is operable to store a second portion of the electric charge corresponding to the detected light intensity. | 07-15-2010 |
20100288927 | Enhanced Direct Injection Circuit - A charge injection circuit is used to control injection of an electronic charge to be added to a photon-induced charge generated by a detector of a direct integration circuit. The electronic charge can be injected directly to the detector or through a parallel path to the detector. Injection of the electronic charge is controlled through one or more switching transistors | 11-18-2010 |
20110141330 | Compensating For Misalignment In An Image Scanner - In certain embodiments, compensating for misalignment comprises receiving, at a detector array, electromagnetic (E-M) radiation from a target object. The detector array comprises time delay and integration (TDI) detectors organized into segments. Each segment comprises one or more rows of detectors perpendicular to a designed scan axis, and comprises columns of detectors parallel to the designed scan axis. The detector array moves in a relative scan direction relative to the target object. The following is performed for each segment and for each column of each segment. If there is misalignment at a segment, a signal is passed to a correcting next column of a next segment in the direction of the misalignment, where the signal accumulates scan data of a portion of the target object. Otherwise, the signal is passed to a designed next column of the next segment in the direction of the designed scan axis. | 06-16-2011 |
20110147878 | High Quantum Efficiency Optical Detectors - An optical detector includes a detector surface operable to receive light, a depleted field region coupled to the underside of the detector surface, a charge collection node underlying the depleted field region, an active pixel area that includes the portion of the depleted field region above the charge collection node and below the detector surface, and two or more guard regions coupled to the underside of the detector surface and outside of the active pixel area. The depleted field region includes an intrinsic or a near-intrinsic material. The charge collection node has a first width, and the guard regions are separated by a second width that is greater than the first width of the charge collection node. The guard regions are operable to prevent crosstalk to an adjacent optical detector. | 06-23-2011 |
20150163401 | Electro-Optical (EO)/Infrared (IR) Staring Focal Planes With High Rate Region of Interest Processing And Event Driven Forensic Look-Back Capability - A focal plane array having: a plurality of detectors; a plurality of unit cell sections, each section being fed by charge produced by corresponding detector for producing a sequence of frames; and a plurality of sets of storage sections, each section being coupled to a corresponding one of the unit cells. Each set of storage sections includes a plurality of storage units for sequentially storing the frames. A region of interest selector section examines the frames of the plurality of unit calls, to detect at least one of the frames having a predetermined characteristic. A processor: (i) identifies a sub-set of the plurality of unit cells proximate the detected unit cells having the predetermined characteristic to establish a region of interest; and (ii) sequentially reads the plurality of storage units in the storage sections coupled to the sub-set of unit cells in the established region of interest. | 06-11-2015 |
20150215536 | SYSTEMS AND METHODS FOR COMBINED STARING AND SCANNING FOCAL PLANE ARRAYS - A combined scanning and staring (SCARING) focal plane array (FPA) imaging system having a plurality of modes of operation is provided. In one example, the SCARING FPA system includes a photodetector array with a plurality of photodetectors arranged in a plurality of photodetector rows, a readout integrated circuit (ROIC) coupled to the photodetector array, and a processor coupled to the ROIC. The processor coupled to the ROIC is configured to dynamically configure the SCARING FPA between a scanning mode of operation and a staring mode of operation. | 07-30-2015 |
20150288907 | METHOD AND SYSTEM FOR MANAGING DEFECTS IN FOCAL PLANE ARRAYS USING REDUNDANT COMPONENTS - A focal plane array having: an imaging array section, comprising: an array of electromagnetic radiation detectors; and an address section providing outputs from selectively enabled detectors. The imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit. Test circuitry is for provided for supplying test signals to test each one of the primary circuits and determining whether a response from the test signals is proper or improper and for storing in the test circuitry in response to such determining select signals associated with each one of the tested circuit blocks. An array controller is provided for, during a subsequent normal operating mode, providing timing pulses to the address section wherein the address section selectively enables the detectors using either the primary or redundant circuits in the plurality of circuit blocks selectively in accordance with the stored select signals. | 10-08-2015 |
Patent application number | Description | Published |
20090146170 | HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching. | 06-11-2009 |
20120104412 | HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching. | 05-03-2012 |
20140346542 | HIGH LIGHT EXTRACTION EFFICIENCY NITRIDE BASED LIGHT EMITTING DIODE BY SURFACE ROUGHENING - A III-nitride light emitting diode (LED) and method of fabricating the same, wherein at least one surface of a semipolar or nonpolar plane of a III-nitride layer of the LED is textured, thereby forming a textured surface in order to increase light extraction. The texturing may be performed by plasma assisted chemical etching, photolithography followed by etching, or nano-imprinting followed by etching. | 11-27-2014 |