Patent application number | Description | Published |
20080244189 | Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access - A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access. | 10-02-2008 |
20080301376 | Method, Apparatus, and System Supporting Improved DMA Writes - A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation. | 12-04-2008 |
20090094385 | Techniques for Handling Commands in an Ordered Command Stream - A technique for handling commands includes assigning respective first tags to ordered commands included in an ordered command stream. Respective second tags are then assigned to subsequent commands that follow an initial command (included in the ordered commands). Each of the respective second tags correspond to one the respective first tags that is associated with an immediate previous one of the ordered commands. The initial command is sent to an execution engine in a first cycle. At least one of the subsequent commands is sent to the execution engine prior to completion of execution of the initial command. | 04-09-2009 |
20090268727 | Early header CRC in data response packets with variable gap count - A method is provided for processing a command issued by a processor over a bus. The method includes ( | 10-29-2009 |
20090268736 | Early header CRC in data response packets with variable gap count - A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus. | 10-29-2009 |
20090271532 | Early header CRC in data response packets with variable gap count - A method is provided for processing a command issued by a processor over a bus. The method includes ( | 10-29-2009 |
20090285222 | Network On Chip With Minimum Guaranteed Bandwidth For Virtual Communications Channels - A network on chip (‘NOC’) with guaranteed minimum bandwidth for virtual communications channels, the NOC including: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, each router coupled for data communications with at least one other router through at least one link, each link including a wire bus wide enough to accommodate simultaneously, for transmission in one direction on the link, all or part of a data switching packet, each router implementing two or more virtual communications channels, each virtual communications channel characterized by a communication type, each virtual communications channel guaranteed at least a minimum bandwidth for data transmissions over a link between routers. | 11-19-2009 |
20110246692 | Implementing Control Using A Single Path In A Multiple Path Interconnect System - A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages. | 10-06-2011 |
20110261815 | Multicasting Using a Multitiered Distributed Virtual Bridge Hierarchy - Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements. | 10-27-2011 |
20110261837 | IMPLEMENTING END-TO-END CREDIT MANAGEMENT FOR ENHANCED LARGE PACKET REASSEMBLY - A method and circuit for implementing end-to-end credit management for enhanced large packet reassembly in an interconnect system, and a design structure on which the subject circuit resides are provided. A transport layer provides buffering and credit control for a super packet received from a source device. A source transport layer sends an End-to-End (ETE) credit request message to a destination transport layer for an outstanding super packet transmission to a destination device. The destination transport layer grants credit to allow at least one source to send a super packet to the destination. The source transport layer fragments the super packet into multiple packets and sends all packets of the super packet only responsive to the credit request being granted by the destination transport layer that is needed to send all packets of the super packet. | 10-27-2011 |
20110283028 | IMPLEMENTING NETWORK MANAGER QUARANTINE MODE - A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval. | 11-17-2011 |
20110283029 | IMPLEMENTING ELECTRONIC CHIP IDENTIFICATION (ECID) EXCHANGE FOR NETWORK SECURITY - A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip. | 11-17-2011 |
20130155850 | BUFFER OCCUPANCY BASED RANDOM SAMPLING FOR CONGESTION MANAGEMENT - A method for buffer occupancy based congestion management includes receiving, by a computing device, a data stream including a plurality of packets from a plurality of sources and storing the packets in a buffer that includes multiple storage units. The method also includes determining if the buffer is congested, responsive to determining that the buffer is congested randomly selecting an occupied unit of the buffer and determining the source of the packet stored in the occupied unit of the buffer and sending a congestion notification message to the source of the packet stored in the occupied unit of the buffer. | 06-20-2013 |
20130155853 | HIERARCHICAL OCCUPANCY-BASED CONGESTION MANAGEMENT - A system for hierarchical occupancy based congestion management includes a buffer embodied in a computer readable storage medium including a plurality of buffer units for storing packets of a data flow received from sources. The system includes a buffer manager that stores information about the packets stored in the buffer, including a selection criterion associated with each of the plurality of sources and a congestion estimator that monitors a congestion level in the buffer. The system also includes a occupancy sampler that randomly selects at least two occupied buffer units from the plurality of buffer units and identifies the source of the packet stored in each of the occupied buffer units and a congestion notification message generator that generates a congestion notification message; wherein if the congestion level in the buffer exceeds a threshold value the congestion notification message is sent to the identified source with a higher selection criteria. | 06-20-2013 |
20130155857 | HYBRID ARRIVAL-OCCUPANCY BASED CONGESTION MANAGEMENT - A method for hybrid arrival-occupancy based congestion management includes increasing a recent arrivals counter associated with a data flow from one or more sources in response to receiving a data packet from one of the sources and storing the data packet in a buffer including multiple storage units. The method includes determining if a buffer is congested, randomly selecting an occupied unit of the buffer and determining the source of the packet stored in the occupied unit of the buffer, generating a congestion notification message, sending the congestion notification message to the source of the packet stored in the occupied unit of the buffer if the recent arrivals counter exceeds a threshold value and decreasing the recent arrivals counter associated with the source of the packet stored in the occupied unit of the buffer and discarding the congestion notification message if the recent arrivals counter has a zero value. | 06-20-2013 |
20130155858 | HIERARCHICAL OCCUPANCY-BASED CONGESTION MANAGEMENT - A method for hierarchical occupancy based congestion management includes receiving, by a computing device, a plurality of data flows, each of the plurality of data flows is received from a source and includes a plurality of data packets and storing the plurality of data packets in a buffer including multiple storage units. The method includes determining if the buffer is congested, responsive to determining the buffer is congested randomly selecting at least two occupied units of the buffer and identifying a source of each of the data packets stored in the occupied units of the buffer and generating a congestion notification message. The method also includes comparing a selection criterion associated with each identified source to determine which identified source has a higher selection criterion and sending the congestion notification message to the identified source with the higher selection criterion. | 06-20-2013 |
20130163611 | FLEXIBLE AND SCALABLE ENHANCED TRANSMISSION SELECTION METHOD FOR NETWORK FABRICS - IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance. | 06-27-2013 |
20130166773 | Flexible and scalable data link layer flow control for network fabrics - A network fabric may divide a physical connection into a plurality of VLANs as defined by IEEE 802.1Q. Moreover, many network fabrics use Priority Flow Control to identify and segregate network traffic based on different traffic classes or priorities. Current routing protocols define only eight traffic classes. In contrast, a network fabric may contain thousands of unique VLANs. When network congestion occurs, network devices (e.g., switches, bridges, routers, servers, etc.) can negotiate to pause the network traffic associated with one of the different traffic classes. Pausing the data packets associated with a single traffic class may also stop the data packets associated with thousands of VLANs. The embodiments disclosed herein permit a network fabric to individually pause VLANs rather than entire traffic classes. | 06-27-2013 |
20130194923 | CONVERGED ENHANCED ETHERNET NETWORK - A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. | 08-01-2013 |
20130194946 | CONVERGED ENHANCED ETHERNET NETWORK - A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. | 08-01-2013 |
20130242985 | MULTICAST BANDWIDTH MULTIPLICATION FOR A UNIFIED DISTRIBUTED SWITCH - The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously. | 09-19-2013 |
20130290559 | DEADLOCK RESOLUTION IN END-TO-END CREDIT PROTOCOL - A method for deadlock resolution in end-to-end credit protocol includes receiving a data frame and determining a number of credits required to transmit the data frame. The method also includes requesting and receiving credits from an end controller and responsively incrementing a credit counter. The method further includes determining if a value of the credit counter is greater than the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is at least the number of credits required, the method includes transmitting the data frame to the end controller and decreasing the value of the credit counter by the number of credits required to transmit the data frame. Based on determining that the value of the credit counter is less than the number of credits required, the method includes transmitting a credit shortage notification to the end controller. | 10-31-2013 |
20130290578 | DEADLOCK RESOLUTION IN END-TO-END CREDIT PROTOCOL - A system for deadlock resolution in end-to-end credit protocol includes a plurality of source controllers configured to receive data frames on an incoming link, wherein each source controller includes a plurality of credit counters. The system also includes a plurality of end controllers configured to receive data frames from the plurality of source controllers, wherein each end controller includes a buffer credit counter, a plurality of request counters, and an output buffer. Each of the plurality of credit counters corresponds to one of the plurality of end controllers and stores a number of credits received from that end controller. The buffer credit counter of each end controller stores a number of available credits of the end controllers. Each of the request counters corresponds to one of the plurality of source controllers and stores a number of credit requests received from that source controller. | 10-31-2013 |
20140204748 | ARBITRATION OF MULTIPLE-THOUSANDS OF FLOWS FOR CONVERGENCE ENHANCED ETHERNET - In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being adapted to: receive a plurality of flows, each flow comprising packets of data, assign a service credit to each of the plurality of flows, assign a weight parameter to each of the plurality of flows, select a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided, wherein a flow is selected from a head of a second control queue when the first control queue is empty or there is indication that the first control queue should be avoided, provide a number of units of service to the selected flow, and decrease the selected flow's service credit by an amount corresponding to the number of units of service provided thereto. | 07-24-2014 |
Patent application number | Description | Published |
20090019228 | Data Cache Invalidate with Data Dependent Expiration Using a Step Value - According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value. | 01-15-2009 |
20110206141 | IMPLEMENTING SERIAL LINK TRAINING PATTERNS SEPARATED BY RANDOM DATA - A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination. | 08-25-2011 |
20110208954 | IMPLEMENTING KNOWN SCRAMBLING RELATIONSHIP AMONG MULTIPLE SERIAL LINKS - A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data. | 08-25-2011 |
20110219139 | USING END-TO-END CREDIT FLOW CONTROL TO REDUCE NUMBER OF VIRTUAL LANES IMPLEMENTED AT LINK AND SWITCH LAYERS - A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified. | 09-08-2011 |
20110228783 | IMPLEMENTING ORDERED AND RELIABLE TRANSFER OF PACKETS WHILE SPRAYING PACKETS OVER MULTIPLE LINKS - A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device. | 09-22-2011 |
20110235652 | IMPLEMENTING ENHANCED LINK BANDWIDTH IN A HEADLESS INTERCONNECT CHIP - A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip. | 09-29-2011 |
20110243154 | USING VARIABLE LENGTH PACKETS TO EMBED EXTRA NETWORK CONTROL INFORMATION - A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet. | 10-06-2011 |
20110261821 | IMPLEMENTING GHOST PACKET REMOVAL WITHIN A RELIABLE MESHED NETWORK - A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device. | 10-27-2011 |