Patent application number | Description | Published |
20130203188 | HYBRID METROLOGY FOR SEMICONDUCTOR DEVICES - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves forming a first feature of the semiconductor device structure on a substrate of semiconductor material, obtaining a first measurement for the semiconductor device structure from a first metrology tool, obtaining a second measurement of the first feature of the semiconductor device structure from a second metrology tool, and determining a hybrid measurement for the first feature based at least in part on the first measurement and the second measurement. | 08-08-2013 |
20130245806 | AUTOMATED HYBRID METROLOGY FOR SEMICONDUCTOR DEVICE FABRICATION - Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe; and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe. | 09-19-2013 |
20140073114 | IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING - Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material. | 03-13-2014 |
20140201693 | AUTOMATING INTEGRATED CIRCUIT DEVICE LIBRARY GENERATION IN MODEL BASED METROLOGY - Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis. | 07-17-2014 |
20140273299 | SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES USING DIFFERENT METROLOGY TOOLS - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information. | 09-18-2014 |
20150033201 | SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute. | 01-29-2015 |
Patent application number | Description | Published |
20080244249 | Managed redundant enterprise basic input/output system store update - A basic input/output system may be stored on two different memories coupled to active management technology firmware and a trusted platform module. The trusted platform module ensures that access to the correct memory. One of the memories is selected to store an update of the basic input/output system. | 10-02-2008 |
20080244257 | Server active management technology (AMT) assisted secure boot - In some embodiments, the invention involves a system and method relating to secure booting of a platform. In at least one embodiment, the present invention is intended to securely boot a platform using one or more signature keys stored in a secure location on the platform, where access to the signature is by a microcontroller on the platform and the host processor has no direct access to alter the signature key. Other embodiments are described and claimed. | 10-02-2008 |
20100262823 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the initiating logical processor if the initiating logical processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 10-14-2010 |
20100281255 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 11-04-2010 |
20110055493 | TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT - The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores. | 03-03-2011 |
20110252203 | TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT - The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores. | 10-13-2011 |
20120239906 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 09-20-2012 |
20130254905 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 09-26-2013 |
20150059007 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 02-26-2015 |
Patent application number | Description | Published |
20100036903 | DISTRIBUTED LOAD BALANCER - Systems and methods that distribute load balancing functionalities in a data center. A network of demultiplexers and load balancer servers enable a calculated scaling and growth operation, wherein capacity of load balancing operation can be adjusted by changing the number of load balancer servers. Accordingly, load balancing functionality/design can be disaggregated to increase resilience and flexibility for both the load balancing and switching mechanisms of the data center. | 02-11-2010 |
20100121865 | LEVERAGING LOW-LATENCY MEMORY ACCESS - Computational units of any task may run in different silos. In an embodiment, a search query may be evaluated efficiently on a non-uniform memory architecture (NUMA) machine, by assigning separate chunks of the index to separate memories. In a NUMA machine, each socket has an attached memory. The latency time is low or high, depending on whether a processor accesses data in its attached memory or a different memory. Copies of an index manager program, which compares a query to an index, run separately on different processors in a NUMA machine. Each instance of the index manager compares the query to the index chunk in the memory attached to the processor on which that instance is running. Thus, each instance of the index manager may compare a query to a particular portion of the index using low-latency accesses, thereby increasing the efficiency of the search. | 05-13-2010 |
20100281482 | APPLICATION EFFICIENCY ENGINE - A system and a method are provided. Performance and capacity statistics, with respect to an application executing on one or more VMs, may be accessed and collected. The collected performance and capacity statistics may be analyzed to determine an improved hardware profile for efficiently executing the application on a VM. VMs with a virtual hardware configuration matching the improved hardware profile may be scheduled and deployed to execute the application. Performance and capacity statistics, with respect to the VMs, may be periodically analyzed to determine whether a threshold condition has occurred. When the threshold condition has been determined to have occurred, performance and capacity statistics, with respect to VMs having different configurations corresponding to different hardware profiles, may be automatically analyzed to determine an updated improved hardware profile. VMs for executing the application may be redeployed with virtual hardware configurations matching the updated improved profile. | 11-04-2010 |
20130120931 | ENCLOSING ARRANGEMENT OF RACKS IN A DATACENTER - Enclosing arrangements of racks of computing devices fully encloses a space, either solely by the racks themselves, or in conjunction with structural features, such as walls and doors. The enclosed space can be either a hot aisle, whose hot air is vented out by fans positioned in at least one vertical extremity of the enclosed space, such as the floor, or ceiling, or it can be a cold aisle, whose cold air is pumped in by those fans. To maintain proper pressurization across a vertical cross-section of the enclosed space, specific ones of the computing devices have their fans adjusted based on their vertical position within the racks or have passive airflow adjustments, such as impedance screens. Computing devices can draw or vent air from their sides, taking advantage of the interstitial space between the racks provided by the enclosing arrangement. | 05-16-2013 |
20140173157 | COMPUTING ENCLOSURE BACKPLANE WITH FLEXIBLE NETWORK SUPPORT - Computing unit enclosures are often configured to connect units (e.g., server racks or trays) with a wired network. Because the network type may vary (e.g., Ethernet, InfiniBand, and Fibre Channel), such enclosures often provide network resources connecting each unit with each supported network type. However, such architectures may present inefficiencies such as unused network resources, and may constrain network support for the units to a small set of supported network types. Presented herein are enclosure architectures enabling flexible and efficient network support by including a backplane comprising a backplane bus that exchanges data between the units and a network adapter using an expansion bus protocol, such as PCI-Express. By shifting the point of network specialization from the enclosure to the network adapter, such architectures may be compatible with network adapters of any network type that communicate with the units according to a widely supported and network-type-independent expansion bus protocol. | 06-19-2014 |
20140189706 | RELIABILITY-AWARE APPLICATION SCHEDULING - Reliability-aware scheduling of processing jobs on one or more processing entities is based on reliability scores assigned to processing entities and minimum acceptable reliability scores of processing jobs. The reliability scores of processing entities are based on independently derived statistical reliability models as applied to reliability data already available from modern computing hardware. Reliability scores of processing entities are continually updated based upon real-time reliability data, as well as prior reliability scores, which are weighted in accordance with the statistical reliability models being utilized. Individual processing jobs specify reliability requirements from which the minimum acceptable reliability score is determined. Such jobs are scheduled on processing entities whose reliability score is greater than or equal to the minimum acceptable reliability score for such jobs. Already scheduled jobs can be rescheduled on other processing entities if reliability scores change. Additionally, a hierarchical scheduling approach can be utilized. | 07-03-2014 |
Patent application number | Description | Published |
20100037935 | Concentrated Photovoltaic System Modules Using III-V Semiconductor Solar Cells - A solar cell module to convert light to electricity. The module may include a housing with a first side and an opposing spaced-apart second side. A plurality of lenses may be positioned on the first side of the housing, and a plurality of solar cell receivers may be positioned on the second side of the housing. Each of the plurality of solar cell receivers may include a III-V compound semiconductor multifunction solar cell. Each may also include a bypass diode coupled with the solar cell. At least one optical element may be positioned above the solar cell to guide the light from one of the lenses onto the solar cell. Each of said solar cell receivers may be disposed in an optical path of one of the lenses. The lens and the at least one optical element may concentrate the light onto the respective solar cell by a factor of 1000 or more to generate in excess of 25 watts of peak power. | 02-18-2010 |
20110155217 | Concentrated Photovoltaic System Modules Using III-V Semiconductor Solar Cells - A solar cell receiver for use in a concentrating solar system which concentrates the solar energy onto a solar cell for converting solar energy to electricity. The solar cell receiver may include a solar cell mounted on a support and with one or more III-V compound semiconductor layers. An optical element may be positioned over the solar cell and have an optical channel with an inlet that faces away from the solar cell and an outlet that faces towards the solar cell. A frame may be positioned over the support and extend around the solar cell with the frame having an inner side that extends above the support and faces towards the optical element. An encapsulant may be positioned over the support and contained between the optical element and the frame. The encapsulant may have enlarged heights at contact points with the optical element and the frame and a reduced height between the contact points away from the optical element and the frame. The solar cell receiver may be used in a solar cell module. | 06-30-2011 |
20110263067 | Methods of Forming a Concentrating Photovoltaic Module - Solar cell modules for converting solar energy into electrical energy. The modules includes a housing formed from three separate members that are attached together to form an interior space. A top member extends across an open side of the housing and includes one or more lenses. One or more solar cell receivers are positioned within the interior space of the house and are aligned with one or more of the lenses to receive and convert the solar energy into electrical energy. | 10-27-2011 |
20130014805 | VENTING ASSEMBLY FOR CONCENTRATING PHOTOVOLTAIC SYSTEM MODULEAANM Vaid; SunilAACI North BrunswickAAST NJAACO USAAGP Vaid; Sunil North Brunswick NJ USAANM Zawadzki; Peter AllenAACI ClintonAAST NJAACO USAAGP Zawadzki; Peter Allen Clinton NJ USAANM Hering; GaryAACI Belle MeadAAST NJAACO USAAGP Hering; Gary Belle Mead NJ USAANM Blumenfeld; PhilipAACI AlbuquerqueAAST NMAACO USAAGP Blumenfeld; Philip Albuquerque NM US - Solar cell modules for converting solar energy into electrical energy, such as used in a concentrating photovoltaic system. The modules have a first ventilating opening in the module housing; and a ventilating subassembly mounted on the module housing and disposed over the ventilating opening in the module housing. The ventilating subassembly has a housing having a first chamber adjacent to and in communication with the first ventilating opening in the module housing; a second chamber adjacent to the first chamber, the second chamber having a second ventilating opening to the external environment; and a filter membrane separating the first chamber from the second chamber to allow air to flow between the first chamber and the second chamber through the filter membrane. | 01-17-2013 |
20150013608 | CERAMIC HEATER - An electrically conductive ceramic heating element for use in a reactor for depositing a film of material onto a semiconductor wafer, said reactor comprising a reactor chamber, a radiative heating device disposed within the reactor chamber including the heating element and operative for heating said wafer to a temperature of greater than 1100 degrees C., a wafer carrier disposed within the reactor chamber and adjacent to the radiative heating device, the wafer carrier having at least one wafer cavity for supporting a semiconductor wafer for having a film of material be deposited thereon. | 01-15-2015 |