Patent application number | Description | Published |
20110127617 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION - In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturing stage, i.e., in the presence of a protective liner material, which may, after forming the extension regions, be patterned into a protective spacer structure used for preserving integrity of the sensitive gate electrode structure. | 06-02-2011 |
20110210380 | CONTACT BARS WITH REDUCED FRINGING CAPACITANCE IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches. | 09-01-2011 |
20110210389 | Transistor Comprising a Buried High-K Metal Gate Electrode Structure - A buried gate electrode structures may be formed in the active regions of sophisticated transistors by providing a recess in the active region and incorporating appropriate gate materials, such as a high-k dielectric material and a metal-containing electrode material. Due to the recessed configuration, the channel length and thus the channel controllability may be increased, without increasing the overall lateral dimensions of the transistor structure. | 09-01-2011 |
20110210427 | STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors. | 09-01-2011 |
20110215415 | Technique for Enhancing Transistor Performance by Transistor Specific Contact Design - By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained. | 09-08-2011 |
20110266633 | Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach - In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches. | 11-03-2011 |
20110269278 | Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices - In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process. | 11-03-2011 |
20110291269 | Semiconductor Device Comprising a Stacked Die Configuration Including an Integrated Peltier Element - In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device. | 12-01-2011 |
20120025266 | Transistors Comprising High-K Metal Gate Electrode Structures and Embedded Strain-Inducing Semiconductor Alloys Formed in a Late Stage - In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration. | 02-02-2012 |