Patent application number | Description | Published |
20080258299 | Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device - A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions. | 10-23-2008 |
20090122178 | CAMERA MODULE AND ELECTRONIC APPARATUS HAVING THE SAME - A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area. | 05-14-2009 |
20090200632 | IMAGE SENSOR HAVING THROUGH VIA - One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal. | 08-13-2009 |
20090256931 | Camera module, method of manufacturing the same, and electronic system having the same - A camera module, a method of manufacturing the same, and an electronic system having the same are provided. The camera module includes an image sensor chip having an active plane and a backside, a ground wiring extending from a sidewall of the image sensor chip to the backside, a lens structure having a light detector with at least one lens stacked on the active plane, and a conductive housing extending to the ground wiring along with an outer wall of the lens structure excluding the light detector. | 10-15-2009 |
20100117181 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip, a transparent substrate, an adhesive pattern, and at least one dew-proofer. The semiconductor includes a pixel area. The transparent substrate is disposed on the semiconductor chip. The adhesive pattern is disposed between the semiconductor chip and the transparent substrate and provides a space on the pixel area. At least one dew-proofer is disposed between the semiconductor chip and the transparent substrate and spaced from the adhesive pattern. | 05-13-2010 |
20100320500 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN EVEN COATING THICKNESS USING ELECTRO-LESS PLATING AND RELATED DEVICE - A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions. | 12-23-2010 |
20110180892 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other. | 07-28-2011 |
20110233706 | Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same - Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer. | 09-29-2011 |
20120018885 | SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS - A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate. | 01-26-2012 |
20120119359 | BUMP STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE - Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump. | 05-17-2012 |
20120133048 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 05-31-2012 |
20120153498 | Semiconductor Device and Method of Forming the Same - In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented. | 06-21-2012 |
20120156823 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth. | 06-21-2012 |
20120168792 | HETEROJUNCTION STRUCTURES OF DIFFERENT SUBSTRATES JOINED AND METHODS OF FABRICATING THE SAME - In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material. | 07-05-2012 |
20130260551 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented. | 10-03-2013 |
20130267057 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other. | 10-10-2013 |
20140057430 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 02-27-2014 |
20140110831 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line. | 04-24-2014 |
20140147974 | BUMP STRUCTURE INCLUDING NANO-WIRES AND A BODY CONNECTING ENDS OF THE NANO-WIRES, SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump. | 05-29-2014 |
20140210075 | METHODS FOR PROCESSING SUBSTRATES - A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer. | 07-31-2014 |
20140213039 | METHODS OF PROCESSING SUBSTRATES - Methods processing substrates are provided. The method may include providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting glue layer and thermosetting release layers provided on opposing sides of the thermosetting glue layer. | 07-31-2014 |
20140252626 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a wafer, a plurality of semiconductor chips each having a connection pad and being stacked on the wafer, resin layers formed to expose top surfaces of the connection pads and to cover lateral surfaces and top surfaces of the semiconductor chips, through lines formed in at least one side of opposite sides of each of the semiconductor chips, to be spaced apart from the semiconductor chips, and to extend in a first direction, and redistribution lines arranged between the through lines, formed to extend in a second direction on the resin layers, and connected to the connection pads, wherein the through lines and the redistribution lines include barrier layers formed on lateral surfaces and bottom surfaces of the through lines and the redistribution lines, and conductive layers formed on the barrier layers. | 09-11-2014 |