Patent application number | Description | Published |
20080203469 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS HAVING DUAL GATE TRANSISTORS - An integrated circuit including an array of memory cells having dual gate transistors with curved current flow, and method for operation and fabrication is disclosed. In one embodiment, in a substrate an array of transistors is formed for selecting one of a plurality of memory cells by selecting a pair of adjacent word lines and a bit line. For minimizing the area of a memory cell and reducing complexity in production an array of dual gate transistors having a curved current flow is disclosed, wherein a small portion of a current is allowed to flow through adjacent memory cells. | 08-28-2008 |
20080205118 | INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE - An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode. | 08-28-2008 |
20080217672 | INTEGRATED CIRCUIT HAVING A MEMORY - An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements. | 09-11-2008 |
20080253160 | INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75. | 10-16-2008 |
20080303013 | INTEGRATED CIRCUIT INCLUDING SPACER DEFINED ELECTRODE - An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode. | 12-11-2008 |
20090127586 | INTEGRATED CIRCUIT HAVING MEMORY CELLS AND METHOD OF MANUFACTURE - An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor. | 05-21-2009 |
20090236658 | ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION - An array of vertical trigate transistors and method of production are disclosed. One embodiment provides an array of selection transistors for selecting one of a plurality of memory cells. A selection transistor is a vertical trigate transistor. | 09-24-2009 |
20090261312 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD - An integrated circuit including an array of low resistive vertical diodes and method. One embodiment provides an array of diodes at least partially formed in a substrate for selecting one of a plurality of memory cells. A diode is coupled to a word line. The word line includes a straight-lined portion and protrusions. The diode includes an active area located between two adjacent protrusions. | 10-22-2009 |
20100027325 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD - An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line. | 02-04-2010 |
20100032635 | ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION - An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench. | 02-11-2010 |
20100061140 | INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING - An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line. | 03-11-2010 |