Patent application number | Description | Published |
20080203386 | Method of forming a patterned resist layer for patterning a semiconductor product - A first embodiment discloses a method of forming a patterned resist layer for patterning a substrate. A resist layer is formed on or above a substrate. An inorganic layer is formed on the resist layer. The resist layer covered with the inorganic layer is lithographically exposed. The resist layer covered with the inorganic layer is patterned by etching, thereby forming a patterned resist layer. | 08-28-2008 |
20090016096 | Integrated Circuits; Method for Manufacturing an Integrated Circuit; Method for Decreasing the Influence of Magnetic Fields; Memory Module - Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature. | 01-15-2009 |
20090072217 | Integrated Circuits; Methods for Manufacturing an Integrated Circuit and Memory Module - Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate having a main processing surface, at least two first electrodes, wherein each of the two first electrodes has a side surface being arranged at a respective angle with regard to the main processing surface, the side surfaces facing one another. The programmable arrangement may further include at least one second electrode and ion conducting material between each of the at least two first electrodes and the at least one second electrode, wherein the at least one second electrode is arranged partially between the side surfaces of the two first electrodes facing one another. | 03-19-2009 |
20090073748 | Integrated Circuits; Methods for Operating an Integrating Circuit; Memory Modules - Embodiments of the invention relate generally to integrated circuits, to methods for operating an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit having a magnetic random access memory cell is provided. The magnetic random access memory cell may include a reference layer structure being polarized in a first direction, a free layer structure including at least two anti-parallel coupled ferromagnetic layers and having an anisotropy in an axis parallel to the first direction, at least one of the at least two anti-parallel coupled ferromagnetic layers being made of a material having a temperature dependent saturation magnetization moment, and a non-magnetic tunnel barrier layer structure being disposed between the reference layer structure and the free layer structure. | 03-19-2009 |
20090073749 | INTEGRATED CIRCUIT, CELL ARRANGEMENT, METHOD OF OPERATING AN INTEGRATED CIRCUIT, MEMORY MODULE - An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state. | 03-19-2009 |
20090097298 | Integrated Circuit, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell - According to one embodiment of the present invention, an integrated circuit includes an arrangement of memory cells. Each memory cell is connected to a programming current path used for programming the memory cell, and a sensing current path used for sensing the memory state of the memory cell. The programming current path and the sensing current path are at least partly separated from each other. | 04-16-2009 |
20090213642 | Integrated Circuit, Memory Cell Arrangement, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing a Memory Cell - According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects. | 08-27-2009 |
20090273966 | Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other. | 11-05-2009 |
20090321860 | INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD - An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
20090322319 | MAGNETORESISTIVE SENSOR WITH TUNNEL BARRIER AND METHOD - Magnetoresistive sensors with tunnel barrier and method. One embodiment provides a magnetoresistive sensor having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 12-31-2009 |
20100013035 | Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer. | 01-21-2010 |