Patent application number | Description | Published |
20100074015 | SENSING FOR MEMORY READ AND PROGRAM VERIFY OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line. | 03-25-2010 |
20100110789 | MEMORY DEVICE BIASING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device. | 05-06-2010 |
20100211733 | DATA VALID INDICATION METHOD AND APPARATUS - Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers. | 08-19-2010 |
20110063919 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 03-17-2011 |
20110310675 | LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells. | 12-22-2011 |
20120170372 | MEMORY DEVICE BIASING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device. | 07-05-2012 |
20120240011 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING - The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | 09-20-2012 |
20130003465 | LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells. | 01-03-2013 |
20130294156 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 11-07-2013 |
20130322170 | MEMORY CELL SENSING - This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data. | 12-05-2013 |
20140068186 | METHODS AND APPARATUS FOR DESIGNATING OR USING DATA STATUS INDICATORS - Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers. | 03-06-2014 |
20140189465 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING - The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | 07-03-2014 |
20140286092 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 09-25-2014 |
20140321202 | DEFECTIVE BLOCK MANAGEMENT - In a flash memory, erase blocks containing shorted or broken word lines may be used, at least in part, to store user data. Such blocks may use different parameters to those used by non-defective blocks, may be subject to different wear leveling, and may store data selected to reduce the number of access operations. | 10-30-2014 |
20150046770 | SENSING PARAMETER MANAGEMENT IN NON-VOLATILE MEMORY STORAGE SYSTEM TO COMPENSATE FOR BROKEN WORD LINES - Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line. | 02-12-2015 |
20150063035 | MEMORY DEVICE BIASING METHOD AND APPARATUS - Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory string source line. For example, alternating data lines are sensed while adjacent data lines are coupled to a common source line of the data lines being sensed. Data line shielding methods and apparatus disclosed can reduce effects of source line bounce occurring during a sense operation of a memory device. | 03-05-2015 |
20150085571 | UPDATING READ VOLTAGES - A data storage device includes a controller that is configured to determine a first read voltage for a first page of a non-volatile memory (e.g., a lower page of a Multi-Level Cell flash memory device). The controller is also configured to determine a second read voltage for a second page (e.g., an upper page) of the non-volatile memory by applying an offset value to the first read voltage. The controller is also configured to store data identifying the first read voltage and the second read voltage. | 03-26-2015 |
20150089324 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |
20150089325 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |