Patent application number | Description | Published |
20110265051 | Method for Substrate Noise Analysis - In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal. | 10-27-2011 |
20120119845 | Balun System and Method - A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers. | 05-17-2012 |
20120133471 | High-k Transformers Extending into Multiple Dielectric Layers - A device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers. | 05-31-2012 |
20120147578 | Radio-Frequency Packaging with Reduced RF Loss - A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices. | 06-14-2012 |
20120286836 | Built-in Self-test Circuit for Voltage Controlled Oscillators - A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal. | 11-15-2012 |
20120286888 | Switched Capacitor Array for Voltage Controlled Oscillator - A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code. | 11-15-2012 |
20130154011 | Methods and Apparatus for Reduced Gate Resistance FinFET - Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed. | 06-20-2013 |
20130288443 | Methods for Reduced Gate Resistance FINFET - Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed. | 10-31-2013 |
20140264635 | RF Switch on High Resistive Substrate - A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. | 09-18-2014 |