Patent application number | Description | Published |
20080241369 | METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER - A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks. | 10-02-2008 |
20080242070 | INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET - Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks. | 10-02-2008 |
20090108366 | Structure And Method To Fabricate Metal Gate High-K Devices - Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer. | 04-30-2009 |
20090302396 | Structure and Method to Fabricate Metal Gate High-K Devices - Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer. | 12-10-2009 |
20100041221 | HIGH PERFORMANCE CMOS CIRCUITS, AND METHODS FOR FABRICATING SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention. | 02-18-2010 |
20100112800 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 05-06-2010 |
20110024712 | PCM With Poly-Emitter BJT Access Devices - A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. | 02-03-2011 |
20110298060 | INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface. | 12-08-2011 |
20120142181 | CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS - Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates. | 06-07-2012 |
20120152352 | PHOTOVOLTAIC DEVICES WITH AN INTERFACIAL GERMANIUM-CONTAINING LAYER AND METHODS FOR FORMING THE SAME - A germanium-containing layer is provided between a p-doped silicon-containing layer and a transparent conductive material layer of a photovoltaic device. The germanium-containing layer can be a p-doped silicon-germanium alloy layer or a germanium layer. The germanium-containing layer has a greater atomic concentration of germanium than the p-doped silicon-containing layer. The presence of the germanium-containing layer has the effect of reducing the series resistance and increasing the shunt resistance of the photovoltaic device, thereby increasing the fill factor and the efficiency of the photovoltaic device. In case a silicon-germanium alloy layer is employed, the closed circuit current density also increases. | 06-21-2012 |
20130221373 | SOLAR CELL MADE USING A BARRIER LAYER BETWEEN P-TYPE AND INTRINSIC LAYERS - A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer. | 08-29-2013 |
20130298971 | COST-EFFICENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS - A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer. | 11-14-2013 |
20130320483 | SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES - Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å. | 12-05-2013 |
20140083506 | EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate. | 03-27-2014 |
20140084252 | DOPED GRAPHENE TRANSPARENT CONDUCTIVE ELECTRODE - Graphene is used as a replacement for indium tin oxide as a transparent conductive electrode which can be used in an organic light emitting diode (OLED) device. Using graphene reduces the cost of manufacturing OLED devices and also makes the OLED device extremely flexible. The graphene is chemically doped so that the work function of the graphene is shifted to a higher value for better hole injection into the OLED device as compared to an OLED device containing an undoped layer of graphene. An interfacial layer comprising a conductive polymer and/or metal oxide can also be used to further reduce the remaining injection barrier. | 03-27-2014 |
20140084253 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 03-27-2014 |
20140087500 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 03-27-2014 |
20140087501 | DOPED GRAPHENE TRANSPARENT CONDUCTIVE ELECTRODE - Graphene is used as a replacement for indium tin oxide as a transparent conductive electrode which can be used in an organic light emitting diode (OLED) device. Using graphene reduces the cost of manufacturing OLED devices and also makes the OLED device extremely flexible. The graphene is chemically doped so that the work function of the graphene is shifted to a higher value for better hole injection into the OLED device as compared to an OLED device containing an undoped layer of graphene. An interfacial layer comprising a conductive polymer and/or metal oxide can also be used to further reduce the remaining injection barrier. | 03-27-2014 |
20140087513 | EMBEDDED JUNCTION IN HETERO-STRUCTURED BACK-SURFACE FIELD FOR PHOTOVOLTAIC DEVICES - A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate. | 03-27-2014 |
20140131770 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 05-15-2014 |
20140134811 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 05-15-2014 |
20140179045 | TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL - A transparent conductive electrode stack containing a work function adjusted carbon-containing material is provided. Specifically, the transparent conductive electrode stack includes a layer of a carbon-containing material and a layer of a work function modifying material. The presence of the work function modifying material in the transparent conductive electrode stack shifts the work function of the layer of carbon-containing material to a higher value for better hole injection into the OLED device as compared to a transparent conductive electrode that includes only a layer of carbon-containing material and no work function modifying material. | 06-26-2014 |
20140353698 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20140353700 | HETEROJUNCTION LIGHT EMITTING DIODE - A method for forming a light emitting device includes forming a monocrystalline III-V emissive layer on a monocrystalline substrate and forming a first doped layer on the emissive layer. A first contact is deposited on the first doped layer. The monocrystalline substrate is removed from the emissive layer by a mechanical process. A second doped layer is formed on the emissive layer on a side from which the substrate has been removed. The second doped layer has a dopant conductivity opposite that of the first doped layer. A second contact is deposited on the second doped layer. | 12-04-2014 |
20140361303 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |
20140361350 | THIN-FILM HYBRID COMPLEMENTARY CIRCUITS - Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level. | 12-11-2014 |