Patent application number | Description | Published |
20120313217 | SEAL RING STRUCTURE WITH CAPACITOR - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate. | 12-13-2012 |
20120326263 | SEMICONDUCTOR DIODE - A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer. | 12-27-2012 |
20130001734 | SCHOTTKY DIODE STRUCTURE - A Schottky diode structure includes a semiconductor substrate having an anode region and a cathode region. A lightly doped region with a predetermined conductivity type is in the semiconductor substrate. A metal contact overlies the lightly doped region and corresponds to the cathode region to serve as a cathode. A metal silicide layer is beneath and electrically connected to the metal contact, wherein the metal silicide layer, directly under the metal contact, is in direct contact with the lightly doped region. A heavily doped region with the predetermined conductivity type is in the lightly doped region and corresponds to the anode region to serve as an anode. | 01-03-2013 |
20130002375 | TRANSMISSION LINE STRUCTURE WITH LOW CROSSTALK - A transmission line structure is disclosed. The structure includes at least one signal transmission line and a pair of ground transmission lines embedded in a first level of a dielectric layer on a substrate, wherein the pair of ground transmission lines are on both sides of the signal transmission line. A first ground layer is embedded in a second level lower than the first level of the dielectric layer and a second ground layer is embedded in a third level higher than the first level of the dielectric layer. First and second pairs of via connectors are embedded in the dielectric layer, wherein the first pair of via connectors electrically connects the pair of ground transmission lines to the first ground layer and the second pair of via connectors electrically connects the pair of ground transmission lines to the second ground layer. | 01-03-2013 |
20130009250 | DUMMY PATTERNS FOR IMPROVING WIDTH DEPENDENT DEVICE MISMATCH IN HIGH-K METAL GATE PROCESS - A semiconductor integrated circuit device including: a diffusion area defined by an isolation region in a substrate; a PMOS transistor comprising a metal gate and a high-k dielectric over the diffusion area and source/drain regions sandwiching the metal gate in a first direction; a plurality of dummy diffusion areas surrounding and spaced apart from the diffusion area; and a plurality of first dummy patterns at the two sides of the PMOS transistor in a second direction perpendicular to the first direction and between the dummy diffusion areas and the diffusion area. | 01-10-2013 |
20130009741 | INTEGRATED CIRCUIT TRANSFORMER - The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern. | 01-10-2013 |
20140070346 | RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole. | 03-13-2014 |
Patent application number | Description | Published |
20130105899 | INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICE WITH REDUCED JUNCTION BREAKDOWN VOLTAGE | 05-02-2013 |
20130265121 | PASSIVE DEVICE CELL AND FABRICATION PROCESS THEREOF - An embodiment of the invention provides a passive device cell. The passive device cell has a substrate layer, a passive device, and an intermediary layer formed between the substrate layer and the passive device. The intermediary layer includes a plurality of LC resonators. | 10-10-2013 |
20140124871 | LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process. | 05-08-2014 |
20140127869 | LATERAL BIPOLAR JUNCTION TRANSISTOR - A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process. | 05-08-2014 |
20140312470 | SEAL RING STRUCTURE WITH CAPACITOR - A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure. | 10-23-2014 |
Patent application number | Description | Published |
20130107947 | Method and System for Video Coding System with Loop Filtering | 05-02-2013 |
20140092986 | Method and Apparatus for Data Compression Using Error Plane Coding - A method and apparatus of image data compression and decompression are disclosed. According to an embodiment of the present invention, the compression method partitions the image data into access units and encodes each access unit into a bitstream according to a target bit budget. Each access unit is encoded using first data compression to generate a first bitstream and the residual data is further encoded using second data compression to generate a second bitstream if the first bitstream is smaller than the target bit budget. In one example, the second data compression comprises bit plane coding applied to bit plane-ordered data, wherein the bit plane-ordered data is generated by scanning from a most significant bit to a least significant bit of the residual data in a bit plane-wise order. The decompression method comprises steps to recover reconstructed data from the first and second bitstreams. | 04-03-2014 |
20140133574 | Method and Apparatus for Sign Data Hiding of Video and Image Data - A method and apparatus for processing transform coefficients for a video coder or encoder is disclosed in the present invention. Embodiments according to the present invention reduce the storage requirement for sign bit hiding (SBH), improve the parallelism of SBH processing or simplify parity checking. Partial quantized transform coefficients (QTCs) of a transform block may be processed before all QTCs of the transform block are received. Zero and non-zero QTCs of a scan block may be processed concurrently and the QTCs of multiple scan blocks in a transform block may also be processed concurrently when computing cost function for SBH compensation. The range for searching for a value-modification QTC may be less than the scan block to be processed. Parity checking on QTCs may be based on least significant bits (LSBs) of all QTCs or all non-zero QTCs of a scan block. | 05-15-2014 |
20140334724 | Method and Apparatus for Residue Transform - A method and apparatus for a multiple-channel image/video coding system are disclosed. A residue generation process is applied to the image/video data to generate residue data. A set of integer operations is applied to the residue data across the input channels to generate residue transformed data having multiple output channels. In one embodiment, the residue transformed data associated with a first output channel is related to the difference between a first residue data associated with a first input channel and a second residue data associated with a second input channel. In another embodiment, the residue transformed data associated with a second output channel is related to the second difference between a threshold and a third residue data associated with a third input channel, and wherein the threshold corresponds to the first truncated or rounded average of the first residue data and the second residue data. | 11-13-2014 |
20150055697 | Method and Apparatus of Transform Process for Video Coding - A method for transform processing in video coding is disclosed. Embodiments according to the present invention reduce the computational complexity of determining transform size for a processing block corresponding to a prediction block or a coding block. The transform size determination is based on encoder information or external information without comparing costs associated with different transform sizes. The encoder information can be the size of the processing block or the prediction information. The external information may correspond to the system bandwidth, the network bandwidth, the system power, the remaining energy of the battery in a mobile device, the timing budget related to performing transform for a given transform size. In another embodiment, the transform for each prediction block is performed only during cost evaluation or only during video data reconstruction. | 02-26-2015 |