Patent application number | Description | Published |
20080244133 | Data processing apparatus and method for arbitrating access to a shared resource - A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group. Responsive to a predetermined event, the arbitration circuitry re-applies the priority ordering operation within at least one priority group prior to a subsequent performance of the priority determination operation. Such an approach has been found to provide a particularly flexible mechanism for performing arbitration, allowing a wide variety of different arbitration schemes to be implemented using the same arbitration hardware. | 10-02-2008 |
20080244299 | Data processing apparatus and method for translating a signal between a first clock domain and a second clock domain - The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Further, enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period. Hence, such a data processing apparatus controls translation of a signal from a fast clock domain to a slow clock domain where the input delay time of the component in the slower clock domain is configured in terms of the fast clock period, thereby enabling the latency to be tuned having regard to the slow clock domain input delay constraints. In an alternative embodiment, a similar arrangement is used to control translation of a signal from a slow domain to a fast clock domain, with the output delay time of the component in the slow clock domain being configured in terms of the fast clock period. | 10-02-2008 |
20080294929 | Data processing apparatus and method for controlling a transfer of payload data over a communication channel - A data processing apparatus and method are provided for controlling a transfer of payload data over a communication channel. The data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data the subject of the transfer in a later clock cycle. A communication channel is provided over which the payload data is passed from the initiator circuitry to the recipient circuitry along with associated transfer control information, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information. Timing easing circuitry located within the communication channel is then used to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered, whereby the number of clock cycles that elapse between the first clock cycle and the later clock cycle is dependent on the specified timing easing value. This hence enables a multi-cycle path to be provided for the transfer of payload data from the initiator circuitry to the recipient circuitry. | 11-27-2008 |
20090287978 | Operating Parameter Control for Integrated Circuit Signal Paths - An integrated circuit ( | 11-19-2009 |
20110035523 | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure - A communication infrastructure for a data processing apparatus, and a method of operation of such a communication infrastructure are provided. The communication infrastructure provides first and second switching circuits interconnected via a bidirectional link. Both of the switching circuits employ a multi-channel communication protocol, such that for each transaction a communication path is established from an initiating master interface to a target slave interface, with that communication path comprising m channels. The m channels comprise one or more forward channels from the initiating master interface to the target slave interface and one or more reverse channels from the target slave interface to the initiating master interface, and handshaking signals are associated with each of the m channels. The bidirectional link comprises n connection lines, where n is less than m, the bidirectional link supporting a first communication path from the first switching circuit to the second switching circuit and a second communication path in an opposite direction from the second switching circuit to the first switching circuit. Control circuitry is used to multiplex at least one forward channel of the first communication path and at least one reverse channel of the second communication path, with the multiplexing being performed in dependence on the handshaking signals associated with the channels to be multiplexed. This allows the 2 | 02-10-2011 |
20120011291 | Apparatus and method for controlling issuing of transaction requests - Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value. | 01-12-2012 |
20130254145 | INTEGRATED CIRCUIT CONVERGING INTERCONNECT MODE CONTROL - An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology. | 09-26-2013 |
20130318270 | ARBITRATION CIRCUITY AND METHOD FOR ARBITRATING BETWEEN A PLURALITY OF REQUESTS FOR ACCESS TO A SHARED RESOURCE - Arbitration circuitry for arbitrating between a plurality W of requests R for access to a shared resource. Included are state bits storage storing I state bits Q and generating 2I output bits comprising the true and compliment values of each stored state bit and routing circuitry for generating a set of mask signals M from the output bits. Grant circuitry receives the set of mask signals and the plurality of requests, and grants access to the shared resource to an asserted request having regard to the priority ordering encoded by the set of mask signals. State bit update circuitry is responsive to a trigger condition to perform an update causing a change in the priority ordering encoded by the set of mask signals. The routing circuitry provides a pattern of connections such that each mask signal in the set is directly connected to one of said output bits. | 11-28-2013 |
20140079074 | SELECTING BETWEEN CONTENDING DATA PACKETS TO LIMIT LATENCY DIFFERENCES BETWEEN SOURCES - An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected. | 03-20-2014 |
20140082121 | MODELLING DEPENDENCIES IN DATA TRAFFIC - A method of modifying timings of data traffic in a test system by introducing dependencies that would arise in response to data requiring access to a resource. The resource receives the data traffic from at least one initiator and is connected via an interconnect to at least one recipient, the resource comprises a buffer for storing pending data related to an access to the resource that cannot currently complete. The method comprises the steps of:
| 03-20-2014 |
20140082215 | ARBITRATING BETWEEN DATA PATHS IN A BUFFERLESS FREE FLOWING INTERCONNECT - An interconnect comprising paths configured to transmit data packets between nodes on a network. The nodes comprise ports for inputting and outputting the data packets to the interconnect. At least two of the paths each have at least a portion configured such that a data packet addressed for output at one of the nodes on one of the paths and not being accepted at the node will continue along the path and on travelling further will return to the node. The at least two paths are balanced paths such that a data packet not accepted at the one of the nodes will return to the node a same predetermined number of clock cycles later whichever of the balanced paths the data packet is traveling along. The one of the nodes comprises an arbiter that is configured to prioritise one of the balanced data paths for output, the arbiter being configured to ensure that a priority changes after the predetermined number of clock cycles, such that a data packet on any of the balanced paths not being accepted for output at the node on a first attempt is guaranteed to have priority on a subsequent return to the node. | 03-20-2014 |
Patent application number | Description | Published |
20140082239 | ARBITRATION CIRCUITRY AND METHOD - Arbitration circuitry | 03-20-2014 |
20140281180 | DATA COHERENCY MANAGEMENT - A data processing system | 09-18-2014 |
20140372646 | RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION - A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices. | 12-18-2014 |
20140372696 | HANDLING WRITE REQUESTS FOR A DATA ARRAY - A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways. | 12-18-2014 |
20150301961 | HAZARD CHECKING CONTROL WITHIN INTERCONNECT CIRCUITRY - A system-on-check integrated circuit | 10-22-2015 |
20150301962 | REORDER BUFFER PERMITTING PARALLEL PROCESSING OPERATIONS WITH REPAIR ON ORDERING HAZARD DETECTION WITHIN INTERCONNECT CIRCUITRY - A system-on-chip integrated circuit | 10-22-2015 |
20150302193 | PARALLEL SNOOP AND HAZARD CHECKING WITH INTERCONNECT CIRCUITRY - A system-on-chip integrated circuitry includes interconnect circuitry for connecting transaction sources with transaction destinations. A buffer circuit buffers a plurality of access transactions received from the transaction sources before they are passed on to respective transaction destinations. Hazard checking circuitry, such as identifier reuse circuitry, performs hazard checks for access transactions in parallel with snoop operations performed by snoop circuitry for managing coherence between data values stored within the plurality of cache memories. The snoop circuitry includes snoop reordering circuitry for permitting reordering of snoop responses. The snoop circuitry may issue a snoop request for a given access transaction in parallel with the hazard checking circuitry performing one or more hazard checks for that transaction. | 10-22-2015 |
20160055085 | ENFORCING ORDERING OF SNOOP TRANSACTIONS IN AN INTERCONNECT FOR AN INTEGRATED CIRCUIT - An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions. | 02-25-2016 |
20160062890 | COHERENCY CHECKING OF INVALIDATE TRANSACTIONS CAUSED BY SNOOP FILTER EVICTION IN AN INTEGRATED CIRCUIT - An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter. | 03-03-2016 |
20160062893 | INTERCONNECT AND METHOD OF MANAGING A SNOOP FILTER FOR AN INTERCONNECT - An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect. | 03-03-2016 |
20160103776 | TRANSACTION RESPONSE MODIFICATION WITHIN INTERCONNECT CIRCUITRY - Interconnect circuitry | 04-14-2016 |