Tu, AZ
Shanghui L. Tu, Phoenix, AZ US
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20080217725 | SCHOTTKY DIODE STRUCTURE WITH MULTI-PORTIONED GUARD RING AND METHOD OF MANUFACTURE - In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material. | 09-11-2008 |
20080290469 | Edge Seal For a Semiconductor Device and Method Therefor - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 11-27-2008 |
20080299751 | SCHOTTKY DIODE AND METHOD THEREFOR - In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance. | 12-04-2008 |
20090267204 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
20090269912 | EDGE SEAL FOR A SEMICONDUCTOR DEVICE AND METHOD THEREFOR - In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening. | 10-29-2009 |
Shanghui Larry Tu, Phoenix, AZ US
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20100140694 | SEMICONDUCTOR DEVICE HAVING SUB-SURFACE TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers. | 06-10-2010 |
Steven Tu, Phoenix, AZ US
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20100023808 | TRANSACTIONAL FLOW MANAGEMENT INTERRUPT DEBUG ARCHITECTURE - According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted. | 01-28-2010 |
20110200308 | DIGITAL IMAGE DECODER WITH INTEGRATED CONCURRENT IMAGE PRESCALER - According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image. | 08-18-2011 |
Steven J. Tu, Phoenix, AZ US
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20080250168 | METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS - Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed. | 10-09-2008 |
20080282008 | System and Apparatus for Early Fixed Latency Subtractive Decoding - Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period. | 11-13-2008 |
20100050019 | TEST ACCESS PORT - Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor. | 02-25-2010 |
20100220232 | PIPELINING TECHNIQUES FOR DEINTERLACING VIDEO INFORMATION - Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed. | 09-02-2010 |