Patent application number | Description | Published |
20120026782 | SEMICONDUCTOR MEMORY DEVICE - In two inverters included in a latch in a memory cell, the source or drain of a PMOS load transistor connected to a memory node is cut off, and the source or drain of an NMOS drive transistor connected to another memory node is cut off, whereby internal data is fixed or permanently stored in the memory cell while ensuring a resistance to damage to the gate of the transistor and without impairing the regularity of the layout. | 02-02-2012 |
20120137083 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell. | 05-31-2012 |
20120147680 | SEMICONDUCTOR MEMORY DEVICE - A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off. | 06-14-2012 |
20130028032 | SEMICONDUCTOR MEMORY DEVICE - A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines. | 01-31-2013 |
20130051163 | DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read. | 02-28-2013 |
20140028362 | INPUT CIRCUIT - A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied. | 01-30-2014 |
20140036613 | SEMICONDUCTOR INTEGRATED CIRCUIT - There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level. | 02-06-2014 |
20140056094 | WORD-LINE ACTIVATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a state where a signal (IN) is at “H” and an NMOS transistor ( | 02-27-2014 |