| Patent application number | Description | Published |
|---|
| 20090046042 | Drive Method for Reducing the Power Consumption of a Flat Display - The present invention provides a method to reduce the power consumption. The method comprises these steps. First, the RGB gray levels of a pixel are decided. Then, the RGB gray level values are transformed to XYZ tristimulus values. The XYZ tristimulus values are transformed to L*a*b* values. Next, the L*′a*′b*′ values are determined based on an acceptable color difference range. The color difference between the L*′a*′b*′ and the L*a*b* is in the color difference range. Finally, the L*′a*′b*′ values are transformed to X′Y′Z′ values and the X′Y′Z′ values are transformed to R′G′B′ gray level values. | 02-19-2009 |
| 20090284706 | FLAT-PANEL DISPLAY DEVICE HAVING TEST ARCHITECTURE - A flat-panel display device having test architecture is disclosed for disposing shorting bars without sacrificing wiring-on-array bus layout area of the outer-lead-bonding region. The flat-panel display device essentially includes a substrate having a plurality of driving integrated-circuit (IC) mounting areas, a plurality of signal lines and transmission lines disposed on the substrate, and a plurality of shorting bars disposed on the driving IC mounting areas. Each shorting bar is coupled to a corresponding signal line and a corresponding transmission line. Furthermore, in order to take out the laser-cutting process in the fabrication of the flat-panel display device for saving production cost, each driving IC mounting area is further disposed with a plurality of transistors for controlling the signal connections between the shorting bars and the signal lines, and also for controlling the signal connections between the shorting bars and the transmission lines. | 11-19-2009 |
| 20100171726 | Display Panel - A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively. | 07-08-2010 |
| 20100245298 | SHIFT REGISTER CAPABLE OF REDUCING COUPLING EFFECT - A shift register has a plurality of shift register units coupled in series. Each shift register includes a pull-up circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift register unit receives an input voltage at the input end and provides an output voltage at the output end. The input circuit transmits the input voltage to the node based on a first clock signal. The pull-up circuit provides the output voltage based on a second clock signal and the voltage level of the node. The pull-down circuit selectively connects the node with the output end according to a third clock signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node for maintaining the voltage level of the node based on the second and third clock signals. | 09-30-2010 |
| 20100260312 | SHIFT REGISTER OF LCD DEVICES - A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage. | 10-14-2010 |
| 20100302215 | LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY PANEL THEREOF - A pixel array of a liquid crystal display panel in a half source driver (HSD) model is provided. Each two pixels adjacent in the array location are connected to different data lines. Accordingly, the liquid crystal display panel adopting the driving manner of the column inversion can achieve the display effect of the dot inversion. Therefore, the present invention can substantially reduce the power consumption of the source driver and decrease the flicker effect. | 12-02-2010 |
| 20110050659 | Pixel Circuit, Active Matrix Organic Light Emitting Diode Display and Driving Method for Pixel Circuit - An exemplary pixel circuit includes an organic light emitting diode (OLED), a storage capacitance, a driving transistor and first through fourth switching transistors. The driving transistor is for generating a pixel current according to a charge amount stored on the storage capacitance to drive the OLED at a predetermined luminance. The on/off states of the first through fourth transistors are controlled by the same control signal. By means of particular electrical connection relationships of the first through fourth transistors in the pixel circuit, the pixel current flowing through the OLED is irrelevant to the power supply voltage and the threshold voltage of the driving transistor but is increased along with the increase of a cross-voltage of the OLED resulting from long-term use. The present invention also provides an active matrix OLED display using the above-mentioned pixel circuit and a driving method for the pixel circuit. | 03-03-2011 |
| 20110058642 | SHIFT REGISTER CIRCUIT AND GATE SIGNAL GENERATION METHOD THEREOF - A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage. | 03-10-2011 |
| 20110148840 | ORGANIC LIGHT EMITTING DISPLAY HAVING PIXEL DATA SELF-RETAINING FUNCTIONALITY - An organic light emitting display includes a current driving unit, an organic light emitting diode and a memory unit. The current driving unit is employed to provide a driving current according to a driving voltage generated therein. The organic light emitting diode generates a light output based on the driving current. The operation of the memory unit is controlled by a first auxiliary power voltage and a second auxiliary power voltage. When the first auxiliary power voltage is greater than the second auxiliary power voltage, the memory unit is enabled to perform a voltage retaining operation on the driving voltage. When the second auxiliary power voltage is greater than the first auxiliary power voltage, the memory unit is disabled for ceasing the voltage retaining operation. | 06-23-2011 |
| 20110157122 | PIXEL STRUCTURE OF ELECTROLUMINESCENT DISPLAY PANEL - A pixel structure of an electroluminescent display panel includes a plurality of sub-pixel columns, first power lines, and second power lines. Each of the first power lines and each of the second power lines are disposed between two adjacent sub-pixel columns. Each first power line is electrically connected to a portion of sub-pixels of a sub-pixel column disposed on one side of the first power line, and a portion of sub-pixels of the other sub-pixel column disposed on the other side of the first power line. Each second power line is electrically connected to a portion of sub-pixels of a sub-pixel column disposed on one side of the second power line, and a portion of sub-pixels of the other sub-pixel column disposed on the other side of the second power line. | 06-30-2011 |
