Tsung-Heng
Tsung-Heng Chang, New Taipei TW
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20160037078 | ELECTRONIC DEVICE WITH MAGNIFYING ELEMENT - An electronic device includes a magnifying element. The magnifying element includes a camera module and a lens module. The camera module includes an image sensor and a lens related to the image sensor. The lens module is mounted on the lens and used as back projection to ensure that the light exit aperture of the lens module is opposite to the entrance aperture of the camera module. The power of magnification of the electronic device with a magnifying element is determined by the design features of the lens module. | 02-04-2016 |
Tsung-Heng Chen, Taipei County TW
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20110191651 | TWO-PLANE ERROR CORRECTION METHOD FOR A MEMORY DEVICE AND THE MEMORY DEVICE THEREOF - In order to correct errors of a first page on one plane in a two-plane NAND flash memory, use data of a second page on another plane to mix the encoding and leverage the error correction code of the first page. Each of the error correction codes of the first page and the second page is divided into an inner correction code and a cross correction code. The inner correction codes are used to correct errors of their own pages and the cross correction codes are used to correct errors of two distinct groups, grouped from the even and odd bytes of the two pages respectively. The second page, with fewer errors, is therefore used to enhance the correcting ability of the first page, without lengthening the error correction code of the first page. | 08-04-2011 |
20120047314 | DATA BACKUP METHOD FOR FLASH MEMORY MODULE AND SOLID STATE DRIVE - A data backup method for a flash memory module is provided. The flash memory module includes a plurality of flash memory units. In the data backup method, a controller is first provided to receive a backup function enabling signal. The controller then configures the flash memory units according to the backup function enabling signal such that at least one of the flash memory units is configured as a backup storage area and the flash memory units that are not in the backup storage area are configured as a main storage area. The controller then checks and receives an updated status of important data in the main storage area and backs up the important data into the backup storage area according to the updated status. Accessing to the backup storage area and accessing to the main storage area by the controller are independent. | 02-23-2012 |
Tsung-Heng Tsai, Min-Hsiung TW
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20100142258 | TEN-TRANSISTOR STATIC RANDOM ACCESS MEMORY ARCHITECTURE - The present invention discloses a 10T SRAM architecture, wherein two symmetric data access paths are added to a 6T SRAM architecture. Each data access path has two transistors, whereby the read signals are no more driven by the memory unit, wherefore the dimensions of the transistors inside the 10T SRAM cell are no more limited by the required driving capability. Thus, the 10T SRAM architecture can use the minimum-size transistors to achieve a higher operation speed and meet the requirement of the high-speed digital circuit. Further, the 10T SRAM cell of the present invention can achieve an SNM-free feature. | 06-10-2010 |
Tsung-Heng Tsai, Chiayi TW
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20130201047 | ZERO-CROSSING-BASED ANALOG-TO-DIGITAL CONVERTER HAVING CURRENT MISMATCH CORRECTION CAPABILITY - A zero-crossing-based analog-to-digital converter having current mismatch correction capability, that can raise resolution, energy efficiency, and sampling rate of a fully differential zero-crossing circuit, is realized through a 90 nm CMOS technology. The circuit is used mainly to correct offset error, to use a current supply separation technology and a digital correction mechanism to correct mismatch among a plurality of current supplies. | 08-08-2013 |
Tsung-Heng Tsai, Minxiong Township TW
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20130241755 | TIMING CALIBRATION CIRCUIT FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED METHOD - A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC) is provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew. | 09-19-2013 |