# Tsuneo Nakata, Kawasaki JP

## Tsuneo Nakata, Kawasaki JP

Patent application number | Description | Published |
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20080312881 | Circuit design data conversion apparatus, circuit design data conversion method, and computer product - A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins. | 12-18-2008 |

20080312890 | SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD - Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output. | 12-18-2008 |

20090182538 | MULTI-OBJECTIVE OPTIMUM DESIGN SUPPORT DEVICE USING MATHEMATICAL PROCESS TECHNIQUE, ITS METHOD AND PROGRAM | 07-16-2009 |

20090182539 | MULTI-OBJECTIVE OPTIMAL DESIGN SUPPORT DEVICE, METHOD AND PROGRAM STORAGE MEDIUM - An objective function can be mathematically approximated using a prescribed number of sample sets of design parameters and sets of a plurality of objective functions computed corresponding to them. A logical expression indicating a relation between or among arbitrary two or three objective functions of the plurality of mathematically approximated objective functions is computed as an inter-objective-function logical expression and a region that the arbitrary objective function values can take is displayed as a feasible region in an objective space corresponding to the arbitrary objective functions. Furthermore, a point or area in a design space corresponding to arbitrary design parameters corresponding to a point or area specified by a user in the displayed feasible region is displayed. | 07-16-2009 |

20090276740 | VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT - In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output. | 11-05-2009 |

20090287965 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 11-19-2009 |

20100153074 | DESIGN SUPPORT APPARATUS - A design support apparatus for determining a plurality of objective functions for modeling an object having a plurality of elements, each of the elements providing variable geometrical parameters, the design support apparatus includes a memory for storing the variable geometrical parameters and a processor for executing a process including: determining boundary information associated with specified geometrical parameters of the elements which indicate a state of contact between the elements, dividing the variable geometrical parameters into a plurality of groups on the basis of the boundary information, and determining the plurality of objective functions for each of the groups by using the variable geometrical parameters. | 06-17-2010 |

20100332195 | MULTI-PURPOSE OPTIMIZATION DESIGN SUPPORT APPARATUS AND METHOD, AND RECORDING MEDIUM STORING PROGRAM - A design support apparatus includes a parameter set generation unit configured to obtain a plurality of types of parameters and sequentially generates parameter sets while sequentially changing each parameter, a design object shape data generation unit configured to generate design object shape data based on the parameter set and initial shape data representing an initial shape of the design object shape, a geometric penalty function value calculation unit configured to calculate a geometric penalty function value indicating suitability of geometric characteristics of the design object shape based on the design object shape data, an objective function calculation control unit configured to determine whether or not the parameter set is used to calculate an objective function based on the geometric penalty function value and an optimal value of the objective function, and an objective function calculation unit configured to calculate the objective function based on the parameter set. | 12-30-2010 |

20110239172 | VERIFICATION SUPPORTING SYSTEM - A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard. | 09-29-2011 |