Tsukude
Masaki Tsukude, Tokyo JP
Patent application number | Description | Published |
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20080205184 | SEMICONDUCTOR MEMORY DEVICE - This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage. | 08-28-2008 |
20080258805 | Semiconductor device having internal power supply voltage generation circuit - The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal. | 10-23-2008 |
20090196326 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively. | 08-06-2009 |
Masaki Tsukude, Hyogo JP
Patent application number | Description | Published |
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20090091997 | SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR MOUNTING ON PORTABLE TERMINAL - A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register. | 04-09-2009 |
20110199844 | Semiconductor Memory Device Suitable for Mounting on a Portable Terminal - A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal. the control is also performed in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access | 08-18-2011 |
Noboru Tsukude, Chiyoda-Ku JP
Patent application number | Description | Published |
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20130251969 | TRANSPARENT PROTECTIVE PLATE, FLAT PANEL DISPLAY, AND PROCESS FOR PRODUCING FLAT PANEL DISPLAY - To provide a transparent protective plate which can easily be attached to a display main body of a flat panel display, and which can suppress e.g. deterioration of properties at the time of attaching. A transparent protective plate to be bonded to a display surface of a display main body of a flat panel display, which comprises a glass substrate having a thickness of from 0.5 to 1.8 mm, and a pressure-sensitive adhesive layer having a thickness of from 20 to 150 μm, comprising a pressure-sensitive adhesive having a pressure-sensitive adhesive strength of at least 0.1 N/25 mm as specified by JIS Z0237, laminated directly or indirectly on the side to be bonded to the display surface of the glass substrate. | 09-26-2013 |