Patent application number | Description | Published |
20080248403 | METHOD AND SYSTEM FOR IMPROVING CRITICAL DIMENSION UNIFORMITY - A method for improving critical dimension uniformity of a wafer includes exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits conditions of focus and exposure dose for each of the first plurality of substrates to form a plurality of perturbed wafers; measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers; averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map; measuring a sidewall angle of the plurality of mask patterns; averaging the sidewall angle measured to form a perturbed sidewall angle map; and providing the perturbed critical dimension map and the perturbed sidewall angle map to an exposure tool. | 10-09-2008 |
20080309892 | IN-LINE PARTICLE DETECTION FOR IMMERSION LITHOGRAPHY - An immersion lithography system, comprising a lens unit configured to project a pattern from an end thereof and onto a wafer, a hood unit configured to confine an immersion fluid to a region of the wafer surrounding the end of the lens unit, a wafer stage configured to position the wafer proximate the end of the lens unit, and at least one of an image capturing apparatus and a scattering light detection apparatus, wherein the image capturing apparatus is coupled to the wafer stage and is configured to capture an image of a surface of the hood unit proximate the wafer stage, and wherein the scattering light detection apparatus is proximate the end of the lens unit and the hood unit and is configured to detect particles on a surface of the wafer stage. | 12-18-2008 |
20090063074 | Mask Haze Early Detection - Detecting haze formation on a mask by obtaining an optical property of the mask and determining progress of the haze formation based on the obtained optical property. | 03-05-2009 |
20100201961 | System For Improving Critical Dimension Uniformity - A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({F | 08-12-2010 |
20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
20120040278 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. | 02-16-2012 |
20120115073 | SUB-RESOLUTION ROD IN THE TRANSITION REGION - The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature. | 05-10-2012 |
20120135600 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G | 05-31-2012 |
20120308112 | EXTRACTION OF SYSTEMATIC DEFECTS - In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided. | 12-06-2012 |
20130130410 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask. | 05-23-2013 |
20130205265 | OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL - A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template. | 08-08-2013 |
20130259358 | SYSTEM AND METHOD FOR ALIGNMENT IN SEMICONDUCTOR DEVICE FABRICATION - A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes | 10-03-2013 |
20140101623 | METHOD OF MERGING COLOR SETS OF LAYOUT - A method includes determining one or more potential merges corresponding to a color set A | 04-10-2014 |
20140252433 | Multi-Layer Metal Contacts - A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact. | 09-11-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140273446 | Method of Patterning a Feature of a Semiconductor Device - A method including forming a first pattern having a first and second feature is described. A masking layer is formed over the first and second features. An opening is patterned in the masking layer. The opening can extend over at least one of the first and second features. The patterned opening is then used to form a third feature (filled trench) between the first and second features. A second pattern is then formed that includes a fourth feature and fifth feature each having an edge defined by the third feature. The first, second, fourth and fifth features may then be used to pattern an underlying layer over the semiconductor substrate. | 09-18-2014 |
20140273456 | Method for Integrated Circuit Patterning - A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings. | 09-18-2014 |
20140282334 | Method and Apparatus for Extracting Systematic Defects - The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects. | 09-18-2014 |
20150040082 | LAYOUT DECOMPOSITION METHOD - A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result. | 02-05-2015 |