| Patent application number | Description | Published |
|---|
| 20080205817 | INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY - For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. | 08-28-2008 |
| 20090298292 | PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY - A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy. | 12-03-2009 |
| 20110130005 | PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY - A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy. | 06-02-2011 |
