Patent application number | Description | Published |
20140019690 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSOR - A request storing unit in a PF port stores an expanded request. A PF port entry selecting unit controls two pre-fetch requests expanded from the expanded request to consecutively be input to a L2-pipe. When only one of the expanded two pre-fetch requests is aborted, the PF port entry selecting unit further controls the requests such that the aborted pre-fetch request is input to the L2-pipe as the highest priority request. Further, the PF port entry selecting unit receives the number of available resources from a resource managing unit in order to select a pre-fetch request to be input to a pipe inputting unit based on the number of available resources. | 01-16-2014 |
20140046979 | COMPUTATIONAL PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND METHOD OF CONTROLLING INFORMATION PROCESSING DEVICE - A computational processing device includes: a computational-processor that outputs access requests to a storage device; a plurality of request-holding-units that respectively hold access requests output by the computational processor according to individual access types, the access types being types of access requests; an arbitration-unit that arbitrates access requests held in the plurality of request holding units; a buffer-unit that includes a plurality of entries that hold data; and a buffer-controller that causes one of the plurality of entries to hold data output by the storage device in response to an access request arbitrated by the arbitration unit, on the basis of a result of comparing, for each access type, a count value that counts, for each access type, the number of entries holding data from among the plurality of entries against a maximum value for the number of entries made to hold data for each access type. | 02-13-2014 |
20140068179 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD - A processor includes a cache memory that holds data from a main storage device. The processor includes a first control unit that controls acquisition of data, and that outputs an input/output request that requests the transfer of the target data. The processor includes a second control unit that controls the cache memory, that determines, when an instruction to transfer the target data and a response output by the first processor on the basis of the input/output request that has been output to the first processor is received, whether the destination of the response is the processor, and that outputs, to the first control unit when the second control unit determines that the destination of the response is the processor, the response and the target data with respect to the input/output request. | 03-06-2014 |
20140068192 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes a plurality of CPU cores, each having an LI cache memory, that executes processing and issues a request, and an L2 cache memory connected to the plurality of CPU cores, the L2 cache memory is configured, when a request which requests a target data held by none of the L1 cache memories contained in the plurality of CPU cores, is a load request that permits other CPU cores, to make a response to the CPU core having sent the request, with non-exclusive information that indicates that the target data is non-exclusive data, together with the target data; and when the request is a load request that forbids other CPU cores, to make a response to the CPU core having sent the request, with exclusive information that indicates that the target data is exclusive, together with the target data. | 03-06-2014 |
20140068194 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSOR - A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a CPU node without being intervened by the memory management part. | 03-06-2014 |
20140089586 | ARITHMETIC PROCESSING UNIT, INFORMATION PROCESSING DEVICE, AND ARITHMETIC PROCESSING UNIT CONTROL METHOD - An L2 cache control unit searches for a cache memory according to a memory access request which is provided from a request storage unit 0 through a CPU core unit, and retains in request storage units 1 and 2 the memory access request that has a cache mistake that has occurred. A bank abort generation unit counts, for each bank, the number of memory access requests to the main storage device, and instructs the L2 cache control unit to interrupt access when any of the number of counted memory access requests exceeds a specified value. According to the instruction, the L2 cache control unit interrupts the processing of the memory access request retained in the request storage unit 0. A main memory control unit issues the memory access request retained in the request storage unit 2 to the main storage device. | 03-27-2014 |
20140089587 | PROCESSOR, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF PROCESSOR - An entry information storing unit | 03-27-2014 |
20140297957 | OPERATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An operation processing apparatus includes an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data acquired from another operation processing apparatus; a main memory to store the first data; and a control unit to include a storing unit to store status of data indicating whether or not the first data is held by another operation processing apparatus and a indicating unit to indicate a transition between the status in which the first data is held by another operation processing apparatus and the status in which the first data is not held thereby, wherein when the indicating unit indicates that the first data is not held by another operation processing apparatus and a data acquisition request occurs for the first data, the control unit skips a process for referring to the status of use of the first data. | 10-02-2014 |
20140297966 | OPERATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An operation processing apparatus connected with another operation processing apparatus including an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory to store the first data, and a control unit to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first and second data, wherein when the setting unit sets the operation processing unit to the non-operating state and receives a notification related to discarding of the first data from another operation processing apparatus, the control unit acquires the first data from the main memory and holds the acquired data in the cache memory. | 10-02-2014 |