# Toru Akishita, Tokyo JP

## Toru Akishita, Tokyo JP

Patent application number | Description | Published |
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20100002872 | DATA TRANSFORMATION APPARATUS, DATA TRANSFORMATION METHOD, AND COMPUTER PROGRAM - A non-linear transformation processing structure having a high implementation efficiency and a high security is realized. Data transformation is performed using a first non-linear transformation part performing non-linear transformation using a plurality of small S-boxes; a linear transformation part receiving all the outputs from the first non-linear transformation part and performing data transformation using a matrix for performing optimal diffusion mappings; and a second non-linear transformation part including a plurality of small non-linear transformation parts that perform non-linear transformation on individual data units into which output data from the linear transformation part is divided. With this structure, appropriate data diffusion can be achieved without excessively increasing a critical path, and a structure with a high implementation efficiency and a high security can be achieved. | 01-07-2010 |

20100008498 | ENCRYPTION PROCESSING APPARATUS, ENCRYPTION METHOD, AND COMPUTER PROGRAM - A common-key blockcipher processing structure that makes analysis of key more difficult and enhances security and implementation efficiency is realized. In a key scheduling part in an encryption processing apparatus that performs common-key blockcipher processing, a secret key is input to an encryption function including a round function employed in an encryption processing part to generate an intermediate key, and the result of performing bijective transformation based on the intermediate key, the secret key, and the like and the result of performing an exclusive-OR operation on the bijective-transformed data are applied to round keys. With this structure, generation of round keys based on the intermediate key generated using the encryption function whose security has been ensured is performed, thereby making it possible to make analysis of the keys more difficult. The structure of the key scheduling part can be simplified, thereby making it possible to improve the implementation efficiency. | 01-14-2010 |

20100014659 | CRYPTOGRAPHIC PROCESSING APPARATUS AND CRYPTOGRAPHIC PROCESSING METHOD, AND COMPUTER PROGRAM - In extended Feistel type common key block cipher processing, a configuration is realized in which an encryption function and a decryption function are commonly used. In a cryptographic processing configuration to which an extended Feistel structure in which the number of data lines d is set to an integer satisfying d≧3 is applied, involution properties, that is, the application of a common function to encryption processing and decryption processing, can be achieved. With a configuration in which round keys are permuted or F-functions are permuted in the decryption processing, processing using a common function can be performed by setting swap functions for the encryption processing and the decryption processing to have the same processing style. | 01-21-2010 |

20100014664 | Cryptographic Processing Apparatus, Cryptographic Processing Method, and Computer Program - To realize a common-key block cipher process configuration with increased difficulty of key analysis and improved security. In a configuration for storing in a register an intermediate key generated by using a secret key transformation process and performing a transformation process on the register-stored data to generate a round key, a process of swapping (permuting) data segments constituting the register-stored data is executed to generate a round key. For example, four data segments are produced so that two sets of data segments having an equal number of bits are set, and a process of swapping the individual data segments is repeatedly executed to generate a plurality of different round keys. With this configuration, the bit array of each round key can be effectively permuted, and round keys with low relevance can be generated. A high-security cryptographic process with increased difficulty of key analysis can be realized. | 01-21-2010 |

20100091991 | CRYPTOGRAPHIC PROCESSING APPARATUS AND CRYPTOGRAPHIC PROCESSING METHOD, AND COMPUTER PROGRAM - A configuration that efficiently executes cryptographic processing to which a plurality of different F-functions are applied is provided. In a configuration that executes cryptographic processing by performing round operations to which different F-functions are selectively applied, a plurality of F-function correspondence tables, each corresponding to one of the F-functions, in which input values and output values or intermediate values are associated with each other are stored in a memory; in accordance with a prescribed cryptographic processing sequence, addresses corresponding to F-functions for the respective rounds are applied to read F-function correspondence tables from the memory; and output values or intermediate values for input values are acquired on the basis of reference to the tables to obtain data transformation results in accordance with the respective F-functions. | 04-15-2010 |

20100104093 | Encryption Processing Apparatus, Encryption Processing Method, and Computer Program - A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus. | 04-29-2010 |

20100183142 | Encryption Processing Apparatus, Encryption Processing Method, and Computer Program - An apparatus and method for performing a high-speed operation in a hyperelliptic curve cryptography process are provided. If a standard divisor having a weight equal to a genus g in the hyperelliptic curve cryptography of genus g is a target divisor of scalar multiplication, a determination as to whether the standard divisor is divisible into a theta divisor defined as a divisor having a weight less than the genus g is determined, and if the standard divisor is divisible, the theta divisor is generated by dividing the standard divisor, and a scalar multiplication executing block performs the scalar multiplication using the theta divisor. With this arrangement, the scalar multiplication is performed at high speed with an amount of calculation reduced, and a high-speed encryption processing operation is thus performed. | 07-22-2010 |

20100272253 | INFORMATION PROCESSING DEVICE, OPERATION VERIFYING METHOD, AND PROGRAM - An information processing device includes a scalar multiplication operating unit calculating, based on a point P on an elliptic curve E defined on a predetermined defined field, a point Q=s·P by scalar-multiplying the point P and an operation verifying unit verifying whether an equation (P+Q)+G=P+(Q+G) holds by using the point P on the elliptic curve E, the point Q=s·P calculated by the scalar multiplication operating unit, and an arbitrary point G on the elliptic curve E. | 10-28-2010 |

20110211688 | DATA CONVERTER, DATA CONVERSION METHOD AND PROGRAM - A construction with an improved compression-function execution section is achieved. A data conversion process with use of a plurality of compression-function execution sections and through a plurality of process sequences in which divided data blocks constituting message data are processed in parallel is executed. Each of the plurality of compression-function execution sections performs a process with use of a message scheduling section which receives a corresponding divided data block of the message data to perform a message scheduling process, and a process with use of a chaining variable processing section which receives both of an output from the message scheduling section and an intermediate value as an output from a preceding processing section to generate output data whose number of bits is same as that of the intermediate value through compression of received data. The plurality of compression-function execution sections, respectively performing parallel processing commonly use one or both of the message scheduling section and the chaining variable processing section, and allow a single message scheduling section or a single chaining variable processing section to be utilized. Downsizing of a hardware configuration and simplification of processing steps are achieved by such a construction. | 09-01-2011 |

20110238636 | DATA CONVERSION DEVICE, DATA CONVERSION METHOD, AND PROGRAM - There is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety. There are provided a stirring processing section performing a data stirring process on input data; and a compression processing section performing a data compression process on input data including data segments which are divisions of message data, the message data being a target of a data conversion. Part of multi-stage compression subsections is configured to perform a data compression process based on both of output of the stirring processing section and the data segments in the message data. There is provided such a configuration that the stirring process is executed at least on fixed timing of a compression processing round of plural rounds and thus, there is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety. | 09-29-2011 |

20110243319 | Data Converter, Data Conversion Method, and Computer Program - A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments. | 10-06-2011 |

20120191986 | CRYPTOGRAPHIC PROCESSING APPARATUS AND CRYPTOGRAPHIC PROCESSING METHOD, AND COMPUTER PROGRAM - In extended Feistel type common key block cipher processing, a configuration is realized in which an encryption function and a decryption function are commonly used. In a cryptographic processing configuration to which an extended Feistel structure in which the number of data lines d is set to an integer satisfying d≧3 is applied, involution properties, that is, the application of a common function to encryption processing and decryption processing, can be achieved. With a configuration in which round keys are permuted or F-functions are permuted in the decryption processing, processing using a common function can be performed by setting swap functions for the encryption processing and the decryption processing to have the same processing style. | 07-26-2012 |

20130083920 | Data Converter, Data Conversion Method, and Computer Program - A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments. | 04-04-2013 |

20130159264 | DATA CONVERSION DEVICE, DATA CONVERSION METHOD, AND PROGRAM - There is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety. There are provided a stirring processing section performing a data stirring process on input data; and a compression processing section performing a data compression process on input data including data segments which are divisions of message data, the message data being a target of a data conversion. Part of multi-stage compression subsections is configured to perform a data compression process based on both of output of the stirring processing section and the data segments in the message data. There is provided such a configuration that the stirring process is executed at least on fixed timing of a compression processing round of plural rounds and thus, there is realized a data conversion device that performs generation of a hash value with improved analysis resistance and a high degree of safety. | 06-20-2013 |

20130244062 | SECONDARY BATTERY CELL, BATTERY PACK, AND ELECTRIC POWER CONSUMPTION DEVICE - Provided is a secondary battery cell that can certainly prevent detachment of an integrated circuit from the secondary battery cell and attachment of the integrated circuit to another secondary battery cell, a battery pack including such secondary battery cells, and an electric power consumption device including such a battery pack. | 09-19-2013 |

20130251144 | ENCRYPTION PROCESSING DEVICE, ENCRYPTION PROCESSING METHOD, AND PROGRAM - A reduction in the size of encryption processing configuration applying generalized Feistel structures is achieved. The encryption processing configuration applies a generalized Feistel structure for dividing and inputting data into multiple lines, and repeatedly executing data transformation processing applying a round function on the data transferred to each line, and during the execution cycle of a matrix operation by a matrix operation executing unit for executing linear transformation processing applying a matrix on the data in a first line, an operation is executed on the matrix operation processing data from the initial cycle and data in a second line. This configuration enables a register to be used for both the storage of the data for the second line and the storage of the results of the matrix operation on the first line of data in progress, a reduction in the total number of registers, and thus a reduction in size. | 09-26-2013 |

20130339753 | ENCRYPTION PROCESSING DEVICE, ENCRYPTION PROCESSING METHOD, AND PROGRAM - Miniaturization of an encryption processing configuration is achieved. Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line, wherein the encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register. The input values for the F function execution unit are calculable by the inverse calculation in the inverse calculation executing unit, which enables a reduction in registers for storing this data. | 12-19-2013 |

20130343546 | ENCRYPTION PROCESSING DEVICE, ENCRYPTION PROCESSING METHOD, AND PROGRAMME - An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines, and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation; and a key scheduling part configured to output round keys to a round calculation executing unit in the encryption processing part. The key scheduling part is a replacement type key scheduling part configured to generate plural round keys or round key configuration data by dividing a secret key stored beforehand into plural parts. The plural round keys are output to a round calculation executing unit sequentially executing in the encryption processing part such that a constant sequence is not repeated. The encryption processing configuration has a high level of security and a high level of resistance to repeated key attacks or other attacks. | 12-26-2013 |

20140003603 | DATA PROCESSING DEVICE, DATA PROCESSING METHOD, AND PROGRAM | 01-02-2014 |

20140192973 | ENCRYPTION PROCESSING APPARATUS, ENCRYPTION PROCESSING METHOD, AND COMPUTER PROGRAM - A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus. | 07-10-2014 |

20140365546 | ARITHMETIC OPERATION DEVICE, CONTROL METHOD, AND PROGRAM - Provided is an arithmetic operation device including a plurality of shift registers each constituted by first to (N+1) | 12-11-2014 |