Patent application number | Description | Published |
20110291292 | Selective Shrinkage of Contact Elements in a Semiconductor Device - In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element. | 12-01-2011 |
20120001323 | Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction - In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses. | 01-05-2012 |
20120001330 | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism - In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced. | 01-05-2012 |
20120001343 | Sophisticated Metallization Systems in Semiconductors Formed by Removing Damaged Dielectric Surface Layers After Forming the Metal Features - In sophisticated semiconductor devices, densely packed metal line layers may be formed on the basis of an ultra low-k dielectric material, wherein corresponding modified portions of increased dielectric constant may be removed in the presence of the metal lines, for instance, by means of a selective wet chemical etch process. Consequently, the metal lines may be provided with desired critical dimensions without having to take into consideration a change of the critical dimensions upon removing the modified material portion, as is the case in conventional strategies. | 01-05-2012 |
20120028470 | Increasing Robustness of a Dual Stress Liner Approach in a Semiconductor Device by Applying a Wet Chemistry - In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced. | 02-02-2012 |
20120153405 | Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance - In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished. | 06-21-2012 |
20120161242 | ENHANCEMENT OF ULTRAVIOLET CURING OF TENSILE STRESS LINER USING REFLECTIVE MATERIALS - A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an optically reflective layer overlying the NMOS transistor structure, forming a layer of tensile stress inducing material overlying the optically reflective layer, and curing the layer of tensile stress inducing material by applying ultraviolet radiation. Some of the ultraviolet radiation directly radiates the layer of tensile stress inducing material and some of the ultraviolet radiation radiates the layer of tensile stress inducing material by reflecting from the optically reflective layer. | 06-28-2012 |
20120181692 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal. | 07-19-2012 |
20120190195 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING LOCAL CONTACTS - Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer. | 07-26-2012 |
20120199980 | INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING INTERCONNECT STRUCTURES - Integrated circuits and methods for fabricating an integrated circuit are provided. A conductive feature is formed in a semiconductor substrate. A layer of ULK or LK dielectric material is formed overlying the conductive feature. An opening having a sidewall surface is etched through the layer of ULK or LK dielectric material. Damage on the sidewall surface resulting from the etching is removed. An ULK or LK dielectric liner is formed overlying the sidewall surface. The ULK or LK dielectric liner along the bottom of the opening is removed to expose the conductive feature. The opening is filled with a metal fill material contacting the conductive feature. | 08-09-2012 |
20120223437 | Semiconductor Device Comprising Metallization Layers of Reduced Interlayer Capacitance by Reducing the Amount of Etch Stop Materials - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 09-06-2012 |
20120235304 | ULTRAVIOLET (UV)-REFLECTING FILM FOR BEOL PROCESSING - Semiconductor devices are formed with a dielectric stack by forming an UV reflecting layer between cured and uncured ULK layers during BEOL processing. Embodiments include forming a first ultra low-k (ULK) layer on a semiconductor element, curing the first ULK layer, forming an ultraviolet (UV) reflecting layer on the first ULK layer, forming a second ULK layer on the UV reflecting layer, and irradiating the second ULK layer with UV light. | 09-20-2012 |
20130102147 | Methods of Forming Conductive Structures in Dielectric Layers on an Integrated Circuit Device - One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening. | 04-25-2013 |
20130108779 | Methods of Filling Voids in Copper Structures | 05-02-2013 |
20130178057 | Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique - Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench. | 07-11-2013 |
20130189822 | METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS - Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions. | 07-25-2013 |
20130302974 | REPLACEMENT GATE ELECTRODE FILL AT REDUCED TEMPERATURES - Generally, the present disclosure is directed to forming conductive metal fill materials in replacement gate electrodes using reduced deposition temperatures. One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor layer, the sacrificial gate structure including a dummy gate electrode, and forming a gate cavity by removing at least the dummy gate electrode from above the semiconductor layer. The disclosed method further includes forming a work-function material of a replacement metal gate electrode in the gate cavity, and forming a conductive metal fill material in the gate cavity and above the work-function material, wherein forming the conductive metal fill material includes performing a material deposition process at a temperature below approximately 450° C. | 11-14-2013 |
20130302989 | REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES - Generally, the present disclosure is directed to methods for reducing line edge roughness in hardmask integration schemes that are used for forming interconnect structures, such as conductive lines and the like. One illustrative method disclosed herein includes, among other things, forming a metal hardmask above a dielectric material and forming a first opening in the metal hardmask, the first opening comprising sidewalls, and the sidewalls having a surface roughness. The disclosed method further includes reducing the surface roughness of the sidewalls, and using the first opening with the sidewalls of reduced surface roughness to form a second opening in the dielectric material. | 11-14-2013 |
20140197544 | SEMICONDUCTOR DEVICE COMPRISING METALLIZATION LAYERS OF REDUCED INTERLAYER CAPACITANCE BY REDUCING THE AMOUNT OF ETCH STOP MATERIALS - Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines. | 07-17-2014 |
20140239503 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer. | 08-28-2014 |
20140264641 | SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS - When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers. | 09-18-2014 |
20140264758 | METHODS OF FORMING A PROTECTION LAYER TO PROTECT A METAL HARD MASK LAYER DURING LITHOGRAPHY REWORKING PROCESSES - One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer. | 09-18-2014 |
20140349479 | METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION - A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution. | 11-27-2014 |
20150076559 | INTEGRATED CIRCUITS WITH STRAINED SILICON AND METHODS FOR FABRICATING SUCH CIRCUITS - Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium. | 03-19-2015 |