Patent application number | Description | Published |
20090014878 | STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS - A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required. | 01-15-2009 |
20090212388 | HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS - A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance. | 08-27-2009 |
20110084393 | METHOD OF FORMING ELECTRODEPOSITED CONTACTS - A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed. | 04-14-2011 |
Patent application number | Description | Published |
20150089638 | SMART METER SECURITY SYSTEM AND METHOD - A system, method and computer program product for protecting utility usage information from utility company users, e.g., power company endpoints. Smart meters monitor endpoint service usage to identify the start of a critical usage period. During critical usage periods the smart meters select and modulates a generic usage pattern by the difference between the pattern and actual usage. Instead of sending actual usage data, the smart meter sends the modulated generic usage pattern to the service provider. The service provider extracts the deltas and determines endpoint service usage from the extracted deltas. | 03-26-2015 |
20150089639 | SMART METER SECURITY SYSTEM AND METHOD - A system, method and computer program product for protecting utility usage information from utility company users, e.g., power company endpoints. Smart meters monitor endpoint service usage to identify the start of a critical usage period. During critical usage periods the smart meters select and modulates a generic usage pattern by the difference between the pattern and actual usage. Instead of sending actual usage data, the smart meter sends the modulated generic usage pattern to the service provider. The service provider extracts the deltas and determines endpoint service usage from the extracted deltas. | 03-26-2015 |
20150089640 | ENDPOINT LOAD REBALANCING CONTROLLER - A endpoint load rebalancing controller, method of controlling endpoint activity to suppress side channel variation and computer program product for controlling endpoint activity for suppressing side channel variation in information from utility company users, e.g., from power company endpoints. The load rebalancing controller monitors period to period endpoint service usage and predicts next period endpoint service usage. Whenever the controller maintains determines that the endpoint usage will exhibit a change that may be sufficient to convey activity information in side channel activity, the controller rebalances activity for the next period. Rebalancing may include shifting off-line execution from one period to another and capping or increasing on-line execution activity. | 03-26-2015 |
20150089657 | ENDPOINT LOAD REBALANCING CONTROLLER - A endpoint load rebalancing controller, method of controlling endpoint activity to suppress side channel variation and computer program product for controlling endpoint activity for suppressing side channel variation in information from utility company users, e.g., from power company endpoints. The load rebalancing controller monitors period to period endpoint service usage and predicts next period endpoint service usage. Whenever the controller maintains determines that the endpoint usage will exhibit a change that may be sufficient to convey activity information in side channel activity, the controller rebalances activity for the next period. Rebalancing may include shifting off-line execution from one period to another and capping or increasing on-line execution activity. | 03-26-2015 |
Patent application number | Description | Published |
20080203137 | SUBSTRATE BONDING METHODS AND SYSTEM INCLUDING MONITORING - Bonding methods and a bonding system including monitoring are disclosed. In one embodiment, a method of monitoring bonding a first and second substrate includes: providing a plurality of piezoelectric sensors to a substrate mounting stage of a substrate bonding system; and monitoring a force change measured by the plurality of piezoelectric sensors induced by a bond front between the first and second substrate during bonding. This method allows real time monitoring of the bonding quality and adjustment of the bonding process parameters. | 08-28-2008 |
20080206977 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 08-28-2008 |
20090321847 | HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers. | 12-31-2009 |
20100133616 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 06-03-2010 |
20100255262 | BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC - Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality. | 10-07-2010 |
20130307139 | BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED - Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality. | 11-21-2013 |
20140097543 | BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED - Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One structure includes: a first substrate having a metal-dielectric pattern on a surface thereof, the metal-dielectric pattern including: a metal having a concave upper surface; and a dielectric having a substantially uniform upper surface, wherein the metal on the first substrate is raised above the dielectric on the first substrate; and a second substrate bonded with the first substrate, the second substrate including: a dielectric; and a metal positioned substantially below the dielectric of the second substrate, wherein the first substrate and the second substrate are bonded only at the metal from the first substrate and the metal from the second substrate. | 04-10-2014 |
20140145264 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 05-29-2014 |
Patent application number | Description | Published |
20120157330 | Trenched Sample Assembly for Detection of Analytes with Electromagnetic Read-Write Heads - Described are embodiments of an invention for a sample assembly with trenches for detection of analytes with electromagnetic read heads. The sample assembly includes an outer layer with at least one sample trench. The sample trench includes a first set of antibodies that are bonded on a first surface of a base layer. Target antigens are bonded with the first set of antibodies, and a second set of antibodies are bonded to the target antigens. Further, the sample trench includes nanoparticles that are bonded to the second set of antibodies. A head module includes a write head for magnetizing nanoparticles and a read sensor for detecting the magnetized nanoparticles, and thus, the target antigens. The sample trench constrains the biological sample, and thus the target antigen, during the preparation and subsequent analysis of the biological sample. Accordingly, the target antigen is aligned with read elements of a head module such that the target antigen is reliably and accurately detected. Further, to ensure reliable and accurate detection, the outer layer is formed with a low friction material allowing the read head to remain in contact with the upper surface of the outer layer during the process of detection. | 06-21-2012 |
20120309111 | BIOSAMPLE PLATE WITH DATA STORAGE AND WIRELESS COMMUNICATION MEANS - Embodiments of the disclosure relate to a biosample plate that includes a memory component for storing information related to the biosample, biosample plate and biosample analysis data, and a wireless communication interface for transferring information to and from the biosample plate. The biosample plate may be used with an analyzing and data recording system such as an electromagnetic tape drive. The disclosed biosample plate facilitates the correlation between a large number of biosample plates and data as data remains with the corresponding biosamples both when the biosample plates are in use and when they are in storage. The wireless communication interface may comprise an antenna disposed in a biosample plate for data transmission to and from the biosample plate by radio signals. | 12-06-2012 |
20120309297 | CARTRIDGE FOR STORING BIOSAMPLE CAPILLARY TUBES AND USE IN AUTOMATED DATA STORAGE SYSTEMS - Embodiments of the disclosure relate to a cartridge that includes slots for storing biosample capillary tubes. The cartridge has the same form factor as data tape cartridges to allow the cartridge to be handled by the same robotic mechanisms that handle data cartridges in an automated tape library. One aspect of the disclosure concerns a cartridge comprising an enclosure that includes a movable door to provide access to a tube holder in the enclosure. The tube holder includes cylindrical holes or slots for receiving capillary tubes which contain biosamples scanned and analyzed an automated tape library. | 12-06-2012 |
20120309298 | CARTRIDGE FOR STORING BIOSAMPLE PLATES AND USE IN AUTOMATED DATA STORAGE SYSTEMS - Embodiments of the disclosure relate to a biosample cartridge that includes storage slots for holding biosample plates. The cartridge has the same form factor as data tape cartridges to allow the cartridge to be handled by the same robotic mechanisms that handle data cartridges in an automated tape library. One aspect of the disclosure concerns a biosample storage cartridge that has a movable door to provide access to inside the cartridge and a plate holder disposed inside the cartridge. The plate holder includes a plurality of slots for receiving biosample plates that are scanned and processed by the automated tape library. | 12-06-2012 |
20120310550 | IDENTIFICATION OF MOLECULES BASED ON FREQUENCY RESPONSES USING ELECTROMAGNETIC WRITE-HEADS AND MAGNETO-RESISTIVE SENSORS - The invention relates to the identification of molecules using electromagnetic write-heads and magneto-resistive sensors. In one embodiment, an electromagnetic write-head magnetically excites a molecule with an alternating magnetic field. A magneto-resistive sensor measures the resonant response of the magnetically excited molecule. A processor compares the resonant response to a table of known responses of different molecules to identify the chemical composition of the target molecule. | 12-06-2012 |