Patent application number | Description | Published |
20080251943 | FLIP CHIP WITH INTERPOSER, AND METHODS OF MAKING SAME - A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material. | 10-16-2008 |
20080284000 | Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 11-20-2008 |
20090039523 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 02-12-2009 |
20090102002 | PACKAGED SEMICONDUCTOR ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor packages, packaged semiconductor devices, methods of manufacturing semiconductor packages, methods of packaging semiconductor devices, and associated systems are disclosed. A semiconductor package in accordance with a particular embodiment includes a die having a first side carrying a first bond site electrically connected to a sensor and/or a transmitter configured to receive and/or transmit radiation signals. The semiconductor package also includes encapsulant material at least partially encapsulating a portion of the die. The semiconductor package includes a conductive path from the first bond site to a second bond site, positioned on a back surface of the encapsulant, which can include through-encapsulant interconnects. A cover can be positioned adjacent to the die and be generally transparent to a target wavelength. | 04-23-2009 |
20090146234 | MICROELECTRONIC IMAGING UNITS HAVING AN INFRARED-ABSORBING LAYER AND ASSOCIATED SYSTEMS AND METHODS - Infrared (IR) absorbing layers and microelectronic imaging units that employ such layers are disclosed herein. In one embodiment, a method of manufacturing a microelectronic imaging unit includes attaching an IR-absorbing lamina having a filler material to a backside die surface of an imager workpiece. An individual imaging die is singulated from the workpiece such that a section of the infrared-absorbing lamina remains attached to the individual imaging die. The individual imaging die is coupled to an interposer substrate with a portion of the IR-absorbing lamina positioned therebetween. In another embodiment, the IR-absorbing lamina is a die attach film and the filler material is carbon black. | 06-11-2009 |
20090256262 | SEMICONDUCTOR DEVICES INCLUDING POROUS INSULATORS - Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties. | 10-15-2009 |
20100013074 | HIGH DENSITY STACKED DIE ASSEMBLIES, STRUCTURES INCORPORATED THEREIN AND METHODS OF FABRICATING THE ASSEMBLIES - A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side thereof supported on a redistribution element formed of a material of substantially similar CTE to that of the dice, and a paddle-less lead frame secured to the redistribution element during fabrication, including encapsulation. The assembly is configured to be substantially vertically symmetrical with respect to inner ends of lead fingers of the lead frame to facilitate uniform encapsulant flow. The semiconductor die assembly may be configured in a package with leads extending from two sides thereof, such as a thin small outline package (TSOP), or four sides thereof, such as a quad flat pack (QFP). | 01-21-2010 |
20100062571 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate. | 03-11-2010 |
20100096761 | SEMICONDUCTOR SUBSTRATE FOR BUILD-UP PACKAGES - The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies. | 04-22-2010 |
20100109149 | FLIP CHIP WITH INTERPOSER, AND METHODS OF MAKING SAME - A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material. | 05-06-2010 |
20100127409 | MICROELECTRONIC DEVICE WAFERS INCLUDING AN IN-SITU MOLDED ADHESIVE, MOLDS FOR IN-SITU MOLDING ADHESIVES ON MICROELECTRONIC DEVICE WAFERS, AND METHODS OF MOLDING ADHESIVES ON MICROELECTRONIC DEVICE WAFERS - A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing in the molds at least a partial vacuum and partially curing the adhesive provides an in-situ molded adhesive that is positioned on the wafer. The adhesives can be in liquid, solid, or other forms prior to molding. During molding, the adhesive can be partially cured by heating or irradiating. | 05-27-2010 |
20100151630 | Methods of Forming Integrated Circuit Packages, and Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 06-17-2010 |
20100230794 | Method For Fabricating Semiconductor Components Using Maskless Back Side Alignment To Conductive Vias - A method for fabricating semiconductor components includes the steps of: providing a semiconductor substrate having a circuit side, a back side and conductive vias; removing portions of the substrate from the back side to expose terminal portions of the conductive vias; depositing a polymer layer on the back side encapsulating the terminal portions; and then planarizing the polymer layer and ends of the terminal portions to form self aligned conductors embedded in the polymer layer. Additional back side elements, such as terminal contacts and back side redistribution conductors, can also be formed in electrical contact with the conductive vias. A semiconductor component includes the semiconductor substrate, the conductive vias, and the back side conductors embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another. | 09-16-2010 |
20100237494 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed. | 09-23-2010 |
20100320585 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 12-23-2010 |
20110169154 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies. | 07-14-2011 |
20110233745 | Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 09-29-2011 |
20110235306 | MULTI-LENS SOLID STATE LIGHTING DEVICES - Solid state lighting (SSL) devices including a plurality of SSL emitters and methods for manufacturing SSL devices are disclosed. Several embodiments of SSL devices in accordance with the technology include a support having a first lead and a second lead, a plurality of individual SSL emitters attached to the support, and a plurality of lenses. Each SSL emitter has a first contact electrically coupled to the first lead of the support and a second contact electrically coupled to the second lead of the support such that the SSL emitters are commonly connected. Each lens has a curved surface and is aligned with a single corresponding SSL emitter. | 09-29-2011 |
20110272822 | Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors - A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another. | 11-10-2011 |
20120305957 | SOLID STATE LIGHTING DEVICES HAVING SIDE REFLECTIVITY AND ASSOCIATED METHODS OF MANUFACTURE - Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies. | 12-06-2012 |
20130240939 | SOLID STATE LIGHTING DEVICES HAVING SIDE REFLECTIVITY AND ASSOCIATED METHODS OF MANUFACTURE - Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies. | 09-19-2013 |
20130330882 | Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 12-12-2013 |
20140175468 | MULTI-LENS SOLID STATE LIGHTING DEVICES - Solid state lighting (SSL) devices including a plurality of SSL emitters and methods for manufacturing SSL devices are disclosed. Several embodiments of SSL devices in accordance with the technology include a support having a first lead and a second lead, a plurality of individual SSL emitters attached to the support, and a plurality of lenses. Each SSL emitter has a first contact electrically coupled to the first lead of the support and a second contact electrically coupled to the second lead of the support such that the SSL emitters are commonly connected. Each lens has a curved surface and is aligned with a single corresponding SSL emitter. | 06-26-2014 |
20140242751 | PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME - A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material. | 08-28-2014 |