| Patent application number | Description | Published |
|---|
| 20090156009 | Method for manufacturing semiconductor device - Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench. | 06-18-2009 |
| 20090212357 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device. A well region ( | 08-27-2009 |
| 20090212375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 08-27-2009 |
| 20090230470 | Semiconductor device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device. | 09-17-2009 |
| 20100187608 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer. | 07-29-2010 |
| 20110065247 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state. | 03-17-2011 |
| 20110079847 | Semiconductor Device - Provided is a semiconductor device capable of easily setting a holding voltage with a low trigger voltage by locally forming a P-type diffusion layer between N-type source and drain diffusion layers of an NMOS transistor having a conventional drain structure used as an electrostatic protective element of the semiconductor device. | 04-07-2011 |
| 20110156138 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 06-30-2011 |
