| Patent application number | Description | Published |
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| 20090237114 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 09-24-2009 |
| 20100301902 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 12-02-2010 |
| 20110216620 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 09-08-2011 |
| Patent application number | Description | Published |
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| 20090314841 | IC CARD AND AUTHENTICATION PROCESSING METHOD IN IC CARD - An IC card has a CPU which performs various operation processing, a data memory which stores internal data, and a working memory which stores the results of the processing. The CPU performs first operation processing on the internal data stored in the data memory and predetermined data for conversion, stores data for collation obtained by the first operation processing on the internal data and the data for conversion in a working memory, performs second operation processing corresponding to the first operation processing on external data received from the external device and the data for collation stored in the working memory, and collates data obtained by the second operation processing with the data for conversion. | 12-24-2009 |
| 20100038435 | INFORMATION STORAGE MEDIUM - An information storage medium is formed of a card main body having a module embedded therein, and the module includes communicating unit for receiving a command from an external device, storing unit for storing a data processing routine including a plurality of check points, and data processing unit for executing processing corresponding to the command in accordance with the data processing routine, storing a plurality of check flags having the same value that varies in accordance with use of the plurality of check points included in the data processing routine, and confirming validity of data processing based on the plurality of stored check flags. | 02-18-2010 |
| 20100240318 | MOBILE ELECTRONIC DEVICE AND CONTROL METHOD OF MOBILE ELECTRONIC DEVICE - A mobile electronic device that transmits and receives data with respect to an external device by wireless communication receives electric power from the external device by wireless and supplies electric power to respective portions of the mobile electronic device. The mobile electronic device includes a transmission/reception unit configured to transmit and receive data with respect to the external device and a plurality of signal processor units configured to subject data transmitted and received by the transmission/reception unit to signal processes according to different communication protocols. The mobile electronic device determines a communication protocol based on data received by the transmission/reception unit, selects one of the plurality of signal processor units based on the determination result, and performs a control operation to cause the transmission/reception unit to transmit and receive data by use of the selected signal processor unit. | 09-23-2010 |
