Patent application number | Description | Published |
20080230818 | NON-VOLATILE MEMORY DEVICE - According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug. | 09-25-2008 |
20080265298 | SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device including: a transistor including: a source, a drain and a gate; first and second plugs on the source and the drain; a third plug on the gate to have a top face higher than that of the first plug; an interlayer insulating film covering the transistor and the first to the third plugs; a ferroelectric capacitor on the interlayer insulating film, one electrode thereof being connected to the first plug; a barrier film covering surfaces of the ferroelectric capacitor and the interlayer insulating film to prevent a substance affecting the ferroelectric capacitor from entering therethrough; and fourth and fifth plugs disposed on the second and the third plugs and connected thereto through connection holes formed in the barrier film. | 10-30-2008 |
20080308902 | SEMICONDUCTOR DEVICE - This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film. | 12-18-2008 |
20090095993 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier film covering at least the ferroelectric capacitor, and a second contact plug being embedded in the interlayer insulator, the second hydrogen barrier film and the first hydrogen barrier film, one end of the second contact plug connecting to the other of the diffusion layers. | 04-16-2009 |
20090127602 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D | 05-21-2009 |
20100012994 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has the ferroelectric capacitor has: a capacitor film formed above the MOS transistor with an interlayer insulating film interposed therebetween; a first capacitor electrode electrically connected to a source region of the MOS transistor and formed in contact with one side wall of the capacitor film; and a second capacitor electrode electrically connected to a drain region of the MOS transistor and formed in contact with the other side wall of the capacitor film, and the capacitor film is composed of a film stack including a plurality of films including a first insulating film intended to orient a film formed on an upper surface thereof in a predetermined direction and a ferroelectric film formed on the first insulating film to be oriented in a direction perpendicular to the semiconductor substrate. | 01-21-2010 |
20100072525 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to a method for manufacturing a semiconductor memory device of the present invention, a capacitor lower electrode film is left on the wiring layer located above a dummy transistor. In this manner, when processing of the capacitors is performed by removing a capacitor upper electrode film and a ferroelectric film, removal of the wiring layer can be prevented, and the connection between the diffusion layer of a select transistor and a bit line can be secured. | 03-25-2010 |
20100072527 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes: a transistor on a semiconductor substrate; an interlayer dielectric film covering the transistor; a ferroelectric capacitor comprising a first upper electrode, a ferroelectric film, and a lower electrode on the interlayer dielectric film; a contact plug which is in the interlayer dielectric film and electrically connects the lower electrode to the transistor; a second upper electrode on the first upper electrode, a side surface of the second upper electrode being formed in a forward tapered shape; and an interconnection electrically connected via the second upper electrode to the first upper electrode. | 03-25-2010 |
20100117128 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, an impurity diffusion layer that is formed at a surface portion of the semiconductor substrate, an interlayer insulating film that is formed on the semiconductor substrate, a contact plug that penetrates the interlayer insulating film, has a top surface formed higher than a top surface of the interlayer insulating film, a region having a convex shape formed higher than the top surface of the interlayer insulating film, and contacts the impurity diffusion layer, a lower capacitor electrode film that is formed on the contact plug and a predetermined region of the interlayer insulating film, a ferroelectric film that is formed on the lower capacitor electrode film, and an upper capacitor electrode film that is formed on the ferroelectric film. | 05-13-2010 |
20100123177 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film. | 05-20-2010 |
20100163943 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer. | 07-01-2010 |
20100193849 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FERROELECTRIC FILM AND A METHOD FOR FABRICATING THE SAME - According to one embodiment, a semiconductor memory device having a ferroelectric film, includes a semiconductor substrate, a field effect transistor formed on the semiconductor substrate, an inter-layer insulating film formed on the field effect transistor and the semiconductor substrate, a plug constituted with a single-crystalline structure, the plug being formed in the inter-layer insulating film and being connected with a source or a drain of the field effect transistor, a lower electrode constituted with a single-crystalline structure formed on the plug, a ferroelectric film formed on the lower electrode an upper electrode formed on the ferroelectric film. | 08-05-2010 |
20110031544 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; an element isolation region formed in the semiconductor substrate so as to extend in a first direction; a gate electrode formed in the semiconductor substrate so as to extend in a second direction crossing the first direction and to penetrate through the element isolation region; a gate insulating film interposed between the gate electrode and the semiconductor substrate; an interlayer dielectric film formed on the gate electrode; a ferroelectric capacitor including: first and second electrodes disposed on the interlayer dielectric film and a ferroelectric between the first and second electrodes; and first and second semiconductor pillars being in contact respectively with the first and second electrodes. | 02-10-2011 |
20120001331 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects. | 01-05-2012 |
20120020158 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more). | 01-26-2012 |
20120139024 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. | 06-07-2012 |