Patent application number | Description | Published |
20140346607 | Tuning Tensile Strain on FinFET - A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin. | 11-27-2014 |
20150034899 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire. | 02-05-2015 |
20150035071 | Semiconductor Device and Fabricating the Same - The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set. | 02-05-2015 |
20150108544 | Fin Spacer Protected Source and Drain Regions in FinFETs - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region. A fin spacer is on a sidewall of the second semiconductor region, wherein the fin spacer overlaps a portion of the insulation regions. | 04-23-2015 |
20150303197 | Semiconductor Device and Fabricating the Same - An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature. | 10-22-2015 |
20160005656 | Fin Spacer Protected Source and Drain Regions in FinFETs - A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin. | 01-07-2016 |
Patent application number | Description | Published |
20090230932 | Quick response width modulation for a voltage regulator - A per-phase quick response generation circuit generates a quick response signal to determine a quick response pulse to be inserted into a pulse width modulation signal of the corresponding phase. The quick response pulse will force the upper power switch of the corresponding phase on to increase the current supply ability during load transition. A multi-phase voltage regulator with the quick response generation circuit can have different quick response pulse widths for the interleaved phases, so as to decrease the current imbalance period of the voltage regulator after load transition. | 09-17-2009 |
20090284239 | Quick response mechanism and method for a switching power system - A quick response mechanism for a switching power system includes a detector and an adjustor connected to the detector. The detector is configured to directly monitor the drop of the output voltage of the switching power system so that a quick response could be immediately triggered when a load transient occurs. The adjustor is configured to adjust the duration of the quick response, thereby preventing the output voltage from undershoot or ringback. | 11-19-2009 |
20120098514 | Current mode switching regulator and control circuit and control method thereof - The present invention discloses a current mode switching regulator, a control circuit of a switching regulator, and a control method of a switching regulator. The switching regulator includes a power stage driven by a driver voltage outputted from a driver circuit. And the power stage switches at least one power transistor to convert an input voltage to an output voltage. The present invention generates an error signal according to a feedback signal related to the output voltage, and adjusts an operation voltage supplied to the driver circuit according to the error signal. | 04-26-2012 |
20120176105 | Multi-phase switching regulator and driver circuit and control method thereof - The present invention discloses a multi-phase switching regulator, a driver circuit of a multi-phase switching regulator, and a control method of a multi-phase switching regulator. The multi-phase switching regulator includes: at least two power stages, switching power transistors in the power stages to convert an input voltage to an output voltage according to pulse width modulation (PWM) signals generated by corresponding PWM controllers respectively; and a current balance circuit, generating a current balance signal according to the current of the corresponding power stage and a phase adjustment signal to averagely distribute current over the active power stages. In the present invention, the gain of the current balance circuit is adjustable, to avoid or reduce output voltage overshoot and undershoot when the phase number changes, while the current balance function is still achieved in normal operation. | 07-12-2012 |
20120235659 | CONTROL CIRCUIT FOR SWITCHING VOLTAGE REGULATOR - A control circuit for a switching voltage regulator is disclosed, having a charging circuit, a discharging circuit, and a charging-discharging control circuit. The charging circuit generates a charging current according to the input voltage and the output voltage of the switching voltage regulator for charging a capacitor. The discharging circuit generates a discharging current according to the output voltage of the switching voltage regulator for discharging the capacitor. The charging-discharging control circuit configures the charging circuit, the discharging circuit, and the switching voltage regulator according to the voltage of the capacitor for providing a control signal to configure the switching voltage regulator. | 09-20-2012 |
20120262136 | ENHANCED PHASE CONTROL CIRCUIT AND METHOD FOR A MULTIPHASE POWER CONVERTER - A multiphase power converter has a plurality of phase circuits, each of which provides a phase current when being active. During single-phase operation of the multiphase power converter, an enhanced phase control circuit and method monitor the summation of the phase currents, and when the summation becomes higher than a threshold, switch the multiphase power converter to a higher power zone to increase the number of active phases. A high efficiency and high reliability multiphase power converter is thus accomplished. | 10-18-2012 |