Patent application number | Description | Published |
20120288089 | SYSTEM AND METHOD FOR DEVICE DEPENDENT AND RATE LIMITED KEY GENERATION - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating a device dependent cryptographic key in a rate-limited way. A system configured to practice the method first receives data associated with a user. The data associated with the user can be a password, a personal identification number (PIN), or a hash of the password. Then the system performs a first encryption operation on the user data based on a device-specific value to yield first intermediate data and performs a second encryption operation on the first intermediate data based on the device-specific value to yield second intermediate data. Then the system iteratively repeats the second encryption operation until a threshold is met, wherein each second encryption operation is performed on the second intermediate data from a previous second encryption operation. The iterations produce a final cryptographic key which the system can then output or use for a cryptographic operation. | 11-15-2012 |
20120306926 | INLINE SCALING UNIT FOR MIRROR MODE - A scaling unit is disclosed that is within a computing device having an internal display and an external interface. The scaling unit facilitates the concurrent presentation of images on the internal display and an external display connected to the external interface. In configurations in which the external interface does not have sufficient data width to concurrently display images on the external display at the same resolution as the internal display, the scaling unit may be used to reduce the number of pixels in a line, thus reducing bandwidth requirements at the external interface. The scaling unit may also scale further to maintain an aspect ratio of the image displayed on the internal display. Further vertical scaling may be performed outside the computing device (e.g., by a dongle coupled between the computing device and the external display), such that the scaling unit may be implemented with reduced memory requirements. | 12-06-2012 |
20120307141 | FRAME RETIMING FOR MIRROR MODE - An inline scaling unit configured to retime an input video frame is disclosed. The scaling unit is configured to receive pixels within a line of a video frame to be displayed on a primary display that is within a first clock domain. The scaling unit down-scales the group of pixels and writes the down-scaled pixels to a buffer circuit in the first clock domain. The scaling unit includes a control circuit configured to generate horizontal and vertical control signals for the retimed video frame to be displayed on a secondary display that is within a second clock domain. The horizontal and vertical control signals are then used to enable reading from the buffer circuit in the second clock domain. The scaling unit outputs the down-scaled pixels and the generated control signals within the retimed video frame such that input video frame and the retimed video frame may be displayed concurrently. | 12-06-2012 |
20130301740 | VIDEO NOISE INJECTION SYSTEM AND METHOD - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 11-14-2013 |
20130332759 | Inter-Processor Communication Channel Including Power-Down Functionality - Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel. | 12-12-2013 |
20150091914 | PROCESSING ORDER IN BLOCK PROCESSING PIPELINES - A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm. | 04-02-2015 |
20150091920 | MEMORY LATENCY TOLERANCE IN BLOCK PROCESSING PIPELINES - Memory latency tolerance methods and apparatus for maintaining an overall level of performance in block processing pipelines that prefetch reference data into a search window. In a general memory latency tolerance method, search window processing in the pipeline may be monitored. If status of search window processing changes in a way that affects pipeline throughput, then pipeline processing may be modified. The modification may be performed according to no stall methods, stall recovery methods, and/or stall prevention methods. In no stall methods, a block may be processed using the data present in the search window without waiting for the missing reference data. In stall recovery methods, the pipeline is allowed to stall, and processing is modified for subsequent blocks to speed up the pipeline and catch up in throughput. In stall prevention methods, processing is adjusted in advance of the pipeline encountering a stall condition. | 04-02-2015 |
20150091921 | WAVEFRONT ENCODING WITH PARALLEL BIT STREAM ENCODING - In the video encoders described herein, blocks of pixels from a video frame may be encoded (e.g., using CAVLC encoding) in a block processing pipeline using wavefront ordering (e.g., in knight's order). Each of the encoded blocks may be written to a particular one of multiple DMA buffers such that the encoded blocks written to each of the buffers represent consecutive blocks of the video frame in scan order. A transcode pipeline may operate in parallel with (or at least overlapping) the operation of the block processing pipeline. The transcode pipeline may read encoded blocks from the buffers in scan order and merge them into a single bit stream (in scan order). A transcoder core of the transcode pipeline may decode the encoded blocks and encode them using a different encoding process (e.g., CABAC). In some cases, the transcoder may be bypassed. | 04-02-2015 |
20150091927 | WAVEFRONT ORDER TO SCAN ORDER SYNCHRONIZATION - Blocks of pixels from a video frame may be encoded in a block processing pipeline using wavefront ordering, e.g. according to knight's order. Each of the encoded blocks may be written to a particular one of multiple buffers such that the blocks written to each of the buffers represent consecutive blocks of the frame in scan order. Stitching information may be written to the buffers at the end of each row. A stitcher may read the rows from the buffers in order and generate a scan order output stream for the frame. The stitcher component may read the stitching information at the end of each row and apply the stitching information to one or more blocks at the beginning of a next row to stitch the next row to the previous row. Stitching may involve modifying pixel(s) of the blocks and/or modifying metadata for the blocks. | 04-02-2015 |
20150092843 | DATA STORAGE AND ACCESS IN BLOCK PROCESSING PIPELINES - Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline. | 04-02-2015 |
20150092854 | PARALLEL HARDWARE AND SOFTWARE BLOCK PROCESSING PIPELINES - A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage. | 04-02-2015 |