Patent application number | Description | Published |
20090240959 | BLOCK BASED POWER MANAGEMENT - A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and sets the actual operating state of the power control domain accordingly. | 09-24-2009 |
20090248910 | CENTRAL DMA WITH ARBITRARY PROCESSING FUNCTIONS - A method and system is disclosed for transforming of data by a DMA controller without first saving the transmitted data on an intermediate medium. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is transformed into a modified state. This transformation may include encryption or decryption of the data. The transformation may also include adding error correction bits to the data through an encoding process or decoding previously encoded data. Upon completion of the transformation, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. Also disclosed is a DMA controller capable of performing the data transformation. | 10-01-2009 |
20090248911 | CLOCK CONTROL FOR DMA BUSSES - A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer. | 10-01-2009 |
20090257507 | SYSTEM AND METHOD FOR MASKING VISUAL COMPRESSION ARTIFACTS IN DECODED VIDEO STREAMS - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 10-15-2009 |
20090313484 | METHOD AND APPARATUS FOR PROLONGING BATTERY LIFE OF A MEDIA PLAYER - A method of operating a media player is provided. In one embodiment the method includes receiving a plurality of initially configured video settings for viewing a video segment on the media player for a desired playback duration. The method further includes determining power required to play the video segment based on the initial video settings and playing the video segment if the required power matches or is less than total power available to the media player. In another embodiment, the method may further include, if the required power exceeds the total power available to the media player, adjusting one or more of the initial video settings, either automatically or by user inputs, to reduce the power required to play the requested video segment for the desired playback duration. | 12-17-2009 |
20100060792 | Video rotation method and device - A media processing system with an improved method and device for rotating a video image is provided. Embodiments of the media processing system include a video decoder with the ability to output decoded video in a landscape or portrait orientation. In some embodiments, the video output orientation is based on the physical orientation of the display as indicated by an electronic sensor. | 03-11-2010 |
20100082849 | Data filtering using central DMA mechanism - A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. | 04-01-2010 |
20100085290 | Use of on-chip frame buffer to improve LCD response time by overdriving - A method and system is disclosed for improving the response time of displays, such as liquid crystal displays (LCDs). The method includes receiving a target picture frame and comparing it to a current picture frame. If the comparison shows that a display may be unable to transition from a current pixel intensity level to a target pixel intensity level within a specified time period, then the pixels that correspond to those current pixel intensities that may not be reach target pixel intensities may be overdriven. This overdriving of one or more pixels may allow the pixel to reach the target pixel intensity within the specified time period. | 04-08-2010 |
20110010502 | Cache Implementing Multiple Replacement Policies - In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy. | 01-13-2011 |
20110010520 | Block-Based Non-Transparent Cache - In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete. | 01-13-2011 |
20110169847 | User Interface Unit for Fetching Only Active Regions of a Frame - A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream. | 07-14-2011 |
20110169848 | Parameter FIFO - A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit. | 07-14-2011 |
20110169849 | Buffer Underrun Handling - A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller. | 07-14-2011 |
20110246806 | BLOCK BASED POWER MANAGEMENT - A system and method is disclosed for efficiently managing power distribution among the various functional blocks used within portable electronic devices. The method includes allowing each functional block to be independently controlled, containing its own low-level software and power controls for setting the local power state of the functional block. For each power control domain in the implementation, hardware uses these local power states and determines and sets the actual operating state of the power control domain accordingly. | 10-06-2011 |
20110252251 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 10-13-2011 |
20120044372 | DUAL IMAGE SENSOR IMAGE PROCESSING SYSTEM AND METHOD - Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner. | 02-23-2012 |
20120046930 | Controller and Fabric Performance Testing - In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric. | 02-23-2012 |
20120084589 | Hardware Dynamic Cache Power Management - In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors. | 04-05-2012 |
20120117282 | DATA FILTERING USING CENTRAL DMA MECHANISM - A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. | 05-10-2012 |
20120144224 | Adjusting a Device Clock Source to Reduce Wireless Communication Interference - Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference. | 06-07-2012 |
20120185703 | Coordinating Performance Parameters in Multiple Circuits - Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles. | 07-19-2012 |
20120278557 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 11-01-2012 |
20120317427 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 12-13-2012 |
20130039432 | SYSTEM AND METHOD FOR MASKING VISUAL COMPRESSION ARTIFACTS IN DECODED VIDEO STREAMS - A technique is provided for processing decoded video data to mask visual compression artifacts resulting from video compression. In accordance with this technique, a hardware block is provided for generating and adding random noise to the decoded video stream. In one embodiment, a random number is generated for each pixel of the decoded video data and compared against one or more threshold values to determine a threshold range. In such an embodiment, a noise addend value is selected based upon the threshold comparison and summed with the current pixel. While the present technique may not eliminate the compression artifacts, the addition of random noise renders the compression artifacts less noticeable to the human eye and, therefore, more aesthetically pleasing to a viewer. | 02-14-2013 |
20130042155 | NON-INTRUSIVE PROCESSOR TRACING - A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller. | 02-14-2013 |
20130061003 | COHERENCE SWITCH FOR I/O TRAFFIC - A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time port of a memory controller. The coherence switch routes non-coherent traffic to a non-real time port of the memory controller. The coherence switch can also dynamically switch traffic between the two paths. The routing of traffic can be configured via a configuration register, and while software can initiate an update to the configuration register, the actual coherence switch hardware will implement the update. Software can write to a software-writeable copy of the configuration register to initiate an update to the flow path to memory for a transaction identifier. The coherence switch detects the update to the software-writeable copy, and then the coherence switch updates the working copy of the configuration register and implements the new routing. | 03-07-2013 |
20130120037 | Agile Clocking with Receiver PLL Management - A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface. | 05-16-2013 |
20130151781 | Cache Implementing Multiple Replacement Policies - In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy. | 06-13-2013 |
20130232364 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 09-05-2013 |
20140025900 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 01-23-2014 |
20140122908 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 05-01-2014 |
20140139535 | Buffer Underrun Handling - A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller. | 05-22-2014 |
20140232732 | Parameter FIFO - A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit. | 08-21-2014 |
20140253570 | Network Display Support in an Integrated Circuit - In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation. | 09-11-2014 |
20140340130 | Clock Generation Using Fixed Dividers and Multiplex Circuits - Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block. | 11-20-2014 |