Patent application number | Description | Published |
20090014800 | SILICON CONTROLLED RECTIFIER DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in the second region in the substrate, and a p type third doped region (PESD implant region) disposed underneath the first doped region in the first region in the substrate. The well is disposed underneath the first region and the second region, and the third doped region isolates the first doped region from the well. | 01-15-2009 |
20090278168 | STRUCTURE OF SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type. | 11-12-2009 |
20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 01-28-2010 |
20100032758 | LDMOS DEVICE FOR ESD PROTECTION CIRCUIT - A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region. | 02-11-2010 |
20100102379 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, two body regions of the first conductivity type, a body connection region of the first conductivity type, two source regions of the second conductivity type, a drain region of the second conductivity type, a channel region, and a gate electrode. The body regions are disposed in the deep well region configured in the substrate. The body connection region is disposed in the deep well region to connect the body regions. Each of the source regions is disposed in the body region. The drain region is disposed in the deep well between the source regions. The channel region is disposed in a portion of the body region. The gate electrode is disposed on the deep well region between the source regions and the drain region and covers the channel region. | 04-29-2010 |
20100148264 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING THE SAME - An ESD protection device including a substrate, a gate structure, a source region, a drain region and a first implanted region is provided. The gate structure includes a gate dielectric layer and a gate sequentially disposed on the substrate. The source region and the drain region are disposed in the substrate beside the gate structure. The first implanted region has the same conductivity type as the drain region. The first implanted region is disposed below the drain region, and the border thereof does not exceed the border of the drain region. | 06-17-2010 |
20110042716 | ESD protection device structure - An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised. | 02-24-2011 |
20120170160 | ESD protection circuit and ESD protection device thereof - The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter. | 07-05-2012 |
20130027821 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch. | 01-31-2013 |
20130088800 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit. | 04-11-2013 |
20130093009 | METHOD OF MANUFACTURING NMOS TRANSISTOR WITH LOW TRIGGER VOLTAGE - A method for forming an NMOS transistor includes forming a P-substrate; forming an N-well on the P-substrate; forming an N-drift region on the N-well; forming an n+ drain on the N-drift region; forming a plurality of first contacts on the n+ drain along a longitudinal direction; forming a P-body on the N-well; forming a source on the P-body, the source including a plurality of n+ doped regions and at least one p+ doped region arranged along the longitudinal direction; forming a plurality of second contacts on the plurality of n+ doped regions and the at least one p+ doped region; forming a polygate on the P-body; and forming a gate oxide between the polygate and the source. | 04-18-2013 |
20130107402 | ELECTROSTATIC PROTECTION CIRCUIT CAPABLE OF PREVENTING LATCH-UP EFFECT | 05-02-2013 |
20130113045 | ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE - An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs. | 05-09-2013 |
20130181211 | METAL OXIDE SEMICONDUCTOR DEVICE - Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate. | 07-18-2013 |
20130207184 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate structure, a source structure and a drain structure. The substrate includes a deep well region, and the gate structure is disposed on the deep well region. The source structure is formed within the deep well and located at a first side of the gate structure. The drain structure is formed within the deep well region and located at a second side of the gate structure. The drain structure includes a first doped region of a first conductivity type, a first electrode and a second doped region of a second conductivity type. The first doped region is located in the deep well region; the first electrode is electrically connected to the first doped region. The second doped region is disposed within the first doped region and between the first electrode and the gate structure. | 08-15-2013 |
20130208379 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers. | 08-15-2013 |
20130250462 | ESD protection circuit and ESD protection device thereof - The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter. | 09-26-2013 |
20140027856 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well. | 01-30-2014 |
20140183596 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers. | 07-03-2014 |
20140183708 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND FABRICATING METHOD THEREOF - A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region. | 07-03-2014 |
20140203367 | Transistor Structure for Electrostatic Discharge Protection - The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region. | 07-24-2014 |
20140284720 | SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 09-25-2014 |
20140300391 | OUTPUT BUFFER - An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor. | 10-09-2014 |
20140319613 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. | 10-30-2014 |
20150014809 | FIN DIODE STRUCTURE - A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type. | 01-15-2015 |
20150054132 | LATERAL BIPOLAR JUNCTION TRANSISTOR AND FABRICATION METHOD THEREOF - Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region. | 02-26-2015 |