Patent application number | Description | Published |
20090200624 | Circuit and photo sensor overlap for backside illumination image sensor - A backside illuminated (“BSI”) imaging sensor pixel includes a photodiode region and pixel circuitry. The photodiode region is disposed within a semiconductor die for accumulating an image charge in response to light incident upon a backside of the BSI imaging sensor pixel. The pixel circuitry includes transistor pixel circuitry disposed within the semiconductor die between a frontside of the semiconductor die and the photodiode region. At least a portion of the pixel circuitry overlaps the photodiode region. | 08-13-2009 |
20090201400 | Backside illuminated image sensor with global shutter and storage capacitor - A backside illuminated imaging sensor pixel includes a photodiode region, a pixel circuitry region, and a storage capacitor. The photodiode region is disposed within a semiconductor die for accumulating an image charge. The pixel circuitry region is disposed on the semiconductor die between a frontside of the semiconductor die and the photodiode region. The pixel circuitry region overlaps at least a portion of the photodiode region. The storage capacitor is included within the pixel circuitry region overlapping the photodiode region and is selectively coupled to the photodiode region to temporarily store image charges accumulated thereon. | 08-13-2009 |
20090272879 | High conversion gain image sensor - An image sensor includes a photosensitive element, a reset circuit, an amplifier transistor, and a current source. The photosensitive element is coupled to generate an image charge in response to incident light and transfer the image charge to a circuit node. The reset circuit is coupled to selectively reset a voltage at the circuit node. The amplifier transistor includes a gate terminal responsive to the voltage at the circuit node. A current source is coupled between a high level power rail and a second terminal of the amplifier transistor. | 11-05-2009 |
20090316030 | Partial row readout for image sensor - An image sensor includes a color filter array, sense amplifiers, multiplexing circuitry, and an output. The color filter array acquires image data using an array of M columns and N rows of pixels. The sense amplifiers are coupled to the color filter array for reading out image data from the color filter array. The multiplexing circuitry couples the sense amplifiers to the color filter array, wherein each sense amplifier is time shared across multiple columns and multiple rows. The output is coupled to receive the image data from the sense amplifiers and output the image data off-chip. | 12-24-2009 |
20100051785 | IMAGE SENSOR WITH PRISMATIC DE-MULTIPLEXING - An image sensor includes a first imaging pixel for a first color having a photosensitive region disposed within a substrate of the image sensor and a second imaging pixel for a second color that is different from the first color having a photosensitive region disposed within the substrate. A refraction element disposed adjacent to the substrate, so that the refraction element refracts light of the first color to the photosensitive region of the first imaging pixel and refracts light of the second color to the photosensitive region of the second imaging pixel. | 03-04-2010 |
20100314667 | CMOS PIXEL WITH DUAL-ELEMENT TRANSFER GATE - Embodiments of a pixel that includes a photosensitive region, a floating diffusion region, and a transistor transfer gate disposed between the photosensitive region and the floating diffusion region. The transfer gate includes first and second transfer gate elements, the first transfer gate element having a different doping than the second transfer gate element. By controlling the doping of the first and second transfer gate elements a transfer gate can be provided with a greater threshold voltage near the photosensitive region and a lesser threshold voltage near the floating diffusion region. Other embodiments, including process embodiments, are disclosed and claimed. | 12-16-2010 |
20110032405 | IMAGE SENSOR WITH TRANSFER GATE HAVING MULTIPLE CHANNEL SUB-REGIONS - An image sensor pixel includes a photosensitive element, a floating diffusion region and a transfer transistor channel region. The transfer transistor channel region is disposed between the photosensitive region and the floating diffusion region. The transfer transistor channel region includes a first channel sub-region having a first doping concentration and a second channel sub-region having a second doping concentration that is different from the first doping concentration. | 02-10-2011 |
20110148523 | OP-AMP SHARING WITH INPUT AND OUTPUT RESET - An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs. | 06-23-2011 |
20110261233 | IMAGING SENSOR HAVING REDUCED COLUMN FIXED PATTERN NOISE - An imaging sensor having reduced column fixed pattern noise includes a plurality of imaging pixels and a column sampling circuit. The plurality of imaging pixels are arranged in a column the column sampling circuit is coupled to the column. A plurality of sampling channels are included in the column sampling circuit, where the column sampling circuit randomly selects a first sampling channel from among the plurality of sampling channels to sample a first data signal from a pixel included in the plurality of imaging pixels and where the column sampling circuit randomly selects a second sampling channel from among the plurality of sampling channels to sample a second data signal from the pixel. | 10-27-2011 |
20120043589 | ENTRENCHED TRANSFER GATE - An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node. | 02-23-2012 |
20120061789 | IMAGE SENSOR WITH IMPROVED NOISE SHIELDING - An image sensor includes a device wafer including a pixel array for capturing image data bonded to a carrier wafer. Signal lines are disposed adjacent to a side of the carrier wafer opposite the device wafer and a metal noise shielding layer is disposed beneath the pixel array within at least one of the device wafer or the carrier wafer to shield the pixel array from noise emanating from the signal lines. A through-silicon-via (“TSV”) extends through the carrier wafer and the metal noise shielding layer and extends into the device wafer to couple to circuitry within the device wafer. Further noising shielding may be provided by highly doping the carrier wafer and/or overlaying the bottom side of the carrier wafer with a low-K dielectric material. | 03-15-2012 |
20120086844 | CIRCUIT AND PHOTO SENSOR OVERLAP FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A method of operation of a backside illuminated (BSI) pixel array includes acquiring an image signal with a first photosensitive region of a first pixel within the BSI pixel array. The image signal is generated in response to light incident upon a backside of the first pixel. The image signal acquired by the first photosensitive region is transferred to pixel circuitry of the first pixel disposed on a frontside of the first pixel opposite the backside. The pixel circuitry at least partially overlaps the first photosensitive region of the first pixel and extends over die real estate above a second photosensitive region of a second pixel adjacent to the first pixel such that the second pixel donates die real estate unused by the second pixel to the first pixel to accommodate larger pixel circuitry than would fit within the first pixel. | 04-12-2012 |
20120113306 | IMAGE SENSOR WITH PIPELINED COLUMN ANALOG-TO-DIGITAL CONVERTERS - An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values. | 05-10-2012 |
20120120300 | Image Sensor with Two Transfer Gate Off Voltage Lines - An apparatus of one aspect includes an array of pixels. Each of the pixels includes a photosensitive element and a transfer transistor coupled with the photosensitive element. Each of the transfer transistors has a transfer gate. The apparatus also includes a first transfer gate off voltage supply conductor and a second transfer gate off voltage supply conductor. A circuit is coupled with the first and second transfer gate off voltage supply conductors. The circuit is operable to couple the first transfer gate off voltage supply conductor to transfer gates of a first subset of the pixels of the array. The circuit is also operable to concurrently couple the second transfer gate off voltage supply conductor to transfer gates of a second subset of the pixels of the array. | 05-17-2012 |
20130089175 | ARITHMETIC COUNTER CIRCUIT, CONFIGURATION AND APPLICATION FOR HIGH PERFORMANCE CMOS IMAGE SENSORS - An arithmetic counter circuit for high performance CMOS image sensors includes a plurality of flip-flops of a plurality of counter stages and a plurality of multiplexers of the plurality of counter stages being coupled to the plurality of flip-flops. Each of the plurality of multiplexers coupled to receive control signals including at least one of a toggle signal, a keep signal, a shift enable signal, or a mode signal. The control signals select the output of each of the plurality of multiplexers. Each of the plurality of flip-flops is coupled to be in one of a toggle state, a keep state, a reset state or a set state based on inputs received from the plurality of multiplexers. Other embodiments are described. | 04-11-2013 |
20130187027 | IMAGE SENSOR WITH INTEGRATED AMBIENT LIGHT DETECTION - An image sensor having an image acquisition mode and an ambient light sensing mode includes a pixel array having pixel cells organized into rows and columns for capturing image data and ambient light data. Readout circuitry is coupled via column bit lines to the pixels cells to read out the image data along the column bit lines. An ambient light detection (“ALD”) unit is selectively coupled to the pixel array to readout the ambient light data and to generate an ambient light signal based on ambient light incident upon the pixel array. Control circuitry is coupled to the pixel array to control time sharing of the pixels cells between the readout circuitry during image acquisition and the ALD unit during ambient light sensing. | 07-25-2013 |
20130188023 | IMAGE SENSOR WITH OPTICAL FILTERS HAVING ALTERNATING POLARIZATION FOR 3D IMAGING - An image sensor for three-dimensional (“3D”) imaging includes a first, a second, and a third pixel unit, where the second pixel unit is disposed between the first and third pixel units. Optical filters included in the pixel units are disposed on a light incident side of the image sensor to filter polarization-encoded light having a first polarization and a second polarization to photosensing regions of the pixel units. The first pixel unit includes a first optical filter having the first polarization, the second pixel unit includes a second optical filter having the second polarization, and the third pixel unit includes a third optical filter having the first polarization. | 07-25-2013 |
20130214375 | PAD AND CIRCUIT LAYOUT FOR SEMICONDUCTOR DEVICES - An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape. | 08-22-2013 |
20130248937 | ENTRENCHED TRANSFER GATE - An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node. | 09-26-2013 |
20130264465 | SHARED TERMINAL OF AN IMAGE SENSOR SYSTEM FOR TRANSFERRING IMAGE DATA AND CONTROL SIGNALS - An example image sensor system includes an image sensor having a first terminal and a host controller coupled to the first terminal. Logic is included in the image sensor system, that when executed transfers analog image data from the image sensor to the host controller through the first terminal of the image sensor and also transfers one or more digital control signals between the image sensor and the host controller through the same first terminal. | 10-10-2013 |
20130264466 | SHARED TERMINAL OF AN IMAGE SENSOR SYSTEM FOR TRANSFERRING CLOCK AND CONTROL SIGNALS - An example image sensor system includes an image sensor having a first terminal and a host controller coupled to the first terminal. Logic is included in the image sensor system, that when executed transfers clock signals from the host controller to the image sensor through the first terminal of the image sensor and also transfers one or more digital control signals between the image sensor and the host controller through the same first terminal. | 10-10-2013 |
20130264688 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer. | 10-10-2013 |
20140008515 | HYBRID ANALOG-TO-DIGITAL CONVERTER HAVING MULTIPLE ADC MODES - A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage. | 01-09-2014 |
20140014813 | INTEGRATED CIRCUIT STACK WITH INTEGRATED ELECTROMAGNETIC INTERFERENCE SHIELDING - An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface. | 01-16-2014 |
20140078277 | ACQUIRING GLOBAL SHUTTER-TYPE VIDEO IMAGES WITH CMOS PIXEL ARRAY BY STROBING LIGHT DURING VERTICAL BLANKING PERIOD IN OTHERWISE DARK ENVIRONMENT - Introduce CMOS pixel array into dark environment and acquiring video image frames. During a first frame, reset each row of pixels sequentially, and one row at a time, and then read each row of pixels sequentially, and one row at a time. During a second frame, reset each row of pixels sequentially, and one row at a time, and then read each row of pixels sequentially, and one row at a time. Control a light source to illuminate the dark environment during at least a portion of a vertical blanking period between the reading of the last row during the first frame and the reading of the first row during the second frame. Control the light source to not illuminate the dark environment: (a) between the reading the first and last rows during the first frame; and (b) between the reading the first and last rows during the second frame. | 03-20-2014 |
20140103411 | STACKED CHIP IMAGE SENSOR WITH LIGHT-SENSITIVE CIRCUIT ELEMENTS ON THE BOTTOM CHIP - An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage. | 04-17-2014 |
20140124889 | DIE SEAL RING FOR INTEGRATED CIRCUIT SYSTEM WITH STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer. | 05-08-2014 |
20140267860 | IMAGE SENSOR WITH SUBSTRATE NOISE ISOLATION - A process including forming an a backside-illuminated (BSI) image sensor in a substrate, the image sensor including a pixel array formed in or near a front surface of the substrate and one or more circuit blocks formed in the substrate near the pixel array, each circuit block including at least one support circuit. An interconnect layer is formed on the front surface of the substrate that includes a dielectric within which are embedded traces and vias, wherein the traces and vias electrically couple the pixel array to at least one of the one or more support circuits. An isolation trench is formed surrounding at least one of the one or more circuit blocks to isolate the pixel array and other circuit blocks from noise generated by the at least one support circuit within the circuit block surrounded by the isolation trench. Other embodiments are disclosed and claimed. | 09-18-2014 |
20140340549 | IMAGE SENSOR WITH FAST INTRA-FRAME FOCUS - A method of focusing an image sensor includes scanning a first portion of an image frame from an image sensor a first time at a first rate to produce first focus data. A second portion of the image frame from the image sensor is scanned at a second rate to read image data from the second portion. The first rate is greater than the second rate. The first portion of the image frame is scanned a second time at the first rate to produce second focus data. The first focus data and the second focus data are compared, and the focus of a lens is adjusted in response to the comparison of the first focus data and the second focus data. | 11-20-2014 |
20150070542 | SHARED TERMINAL OF AN IMAGE SENSOR SYSTEM FOR TRANSFERRING IMAGE DATA AND CONTROL SIGNALS - An image sensor system includes an image sensor and a host controller. The image sensor includes a power input terminal, a data terminal, a clock input terminal, and a ground terminal. The host controller is coupled to the power input terminal to provide power to the image sensor, the data terminal to receive analog image data from the image sensor, the clock input terminal to provide a clock signal to the image sensor, and the ground terminal. The ground terminal serves as a common reference between the image sensor and one or more circuits of the host controller. The system also includes logic that is configured to transfer the analog image data from the image sensor to the host controller through the data terminal of the image sensor and to transfer one or more digital control signals between the image sensor and the host controller through the data terminal. | 03-12-2015 |
20150070547 | METHOD AND APPARATUS FOR READING IMAGE DATA FROM AN IMAGE SENSOR - A method of reading image data from an image sensor includes accumulating image charges in photosensitive elements of an array of pixel cells. The accumulated image charges are transferred to corresponding transistors in multi-phase transfer channels that are coupled to corresponding columns of the pixel array. Multi-phase transfer signals are generated. Each set of the multi-phase transfer signals includes a plurality of control signals that are out-of-phase with one another and are coupled to control respective transistors in the multi-phase transfer channels. The accumulated image charges from a first variable number of pixel cells of a selected column are output in response to the multi-phase transfer signals. The accumulated image charges from a second variable number of pixel cells of another selected column are output in response to the multi-phase transfer signals. | 03-12-2015 |