Patent application number | Description | Published |
20090114968 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 05-07-2009 |
20090189251 | CAPACITOR FORMATION FOR A PUMPING CIRCUIT - A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode. | 07-30-2009 |
20110241093 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously. | 10-06-2011 |
20110256697 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 10-20-2011 |
Patent application number | Description | Published |
20120256230 | POWER DEVICE WITH TRENCHED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT. | 10-11-2012 |
20120256255 | RECESSED TRENCH GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A recessed trench gate structure is provided. The recessed trench gate structure includes a substrate with a recessed trench, a gate dielectric layer disposed around an inner surface of the recessed trench, a lower gate conductor disposed at a lower portion of the recessed trench and on the gate dielectric layer. Specially, the lower gate conductor has a convex top surface. A spacer is disposed along an inner side wall of a upper portion of the recessed trench and a upper gate conductor is disposed on the lower gate conductor. The convex top surface can prevent the electric field from distributing not uniformly, so that the GIDL can be prevented. | 10-11-2012 |
20120256256 | RECESSED GATE TRANSISTOR WITH CYLINDRICAL FINS - A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction. | 10-11-2012 |
20120256257 | TRANSISTOR WITH BURIED FINS - The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical. | 10-11-2012 |
20120256279 | METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR - A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed. | 10-11-2012 |
20120273874 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 11-01-2012 |
20120299185 | Slit Recess Channel Gate and Method of Forming the Same - A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate. | 11-29-2012 |
20130161734 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A buried channel transistor has a semiconductor substrate, a trench and a doped region. The semiconductor substrate has a first surface and a well under the first surface. The trench is disposed in the semiconductor substrate and extends from the first surface into the well. The trench includes a buried gate structure inside the trench. The buried gate structure has a first workfunction layer, a second workfunction layer with a dopant type opposite to that of the first workfunction layer. The second workfunction layer is disposed adjacent to the first workfunction layer. The buried gate structure further includes a dielectric layer adjacent to the trench inner sidewall. The dielectric layer separates the workfunction layers from the semiconductor substrate. The doped region is disposed in the semiconductor substrate and located above the well. The dopant type of the doped region is opposite to that of the first workfunction layer. | 06-27-2013 |
20130181277 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device includes a semiconductor substrate having a first opening and a second opening adjacent thereto. A first dielectric layer is disposed in a lower portion of the first opening. A charge-trapping dielectric layer is disposed in an upper portion of the first opening to cover the first dielectric layer. A doping region of a predetermined conductivity type is formed in the semiconductor substrate adjacent to the first opening and the second opening, wherein the doping region of the predetermined conductivity type has a polarity which is different from that of the charges trapped in the charge-trapping dielectric layer. A gate electrode is disposed in a lower portion of the second opening. A method for fabricating the semiconductor device is also disclosed. | 07-18-2013 |
20130307067 | Slit Recess Channel Gate - A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. | 11-21-2013 |
20140213027 | MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF - A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line. | 07-31-2014 |
20150123195 | RECESSED CHANNEL ACCESS TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF - A recessed channel access transistor device is provided. A semiconductor substrate having thereon a trench is provided. The trench extends from a main surface of the semiconductor substrate to a predetermined depth. A buried gate electrode is disposed at a lower portion of the trench. A gate oxide layer is formed between the buried gate electrode and the semiconductor substrate. A drain doping region on a first side (cell side) of the trench in the semiconductor substrate and a source doping region on a second side (digit side) of the trench are formed. The source doping region has a junction depth that is deeper than that of the drain doping region. An L-shaped channel is defined along a sidewall surface on the first side and along a bottom surface of the trench between the drain doping region and the source doping region. | 05-07-2015 |