Patent application number | Description | Published |
20090310398 | LOW POWER, SMALL SIZE SRAM ARCHITECTURE - A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl) | 12-17-2009 |
20130242677 | Methods and Apparatus for Designing and Constructing Multi-port Memory Circuits with Voltage Assist - To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the V | 09-19-2013 |
20130258757 | Methods And Apparatus For Synthesizing Multi-Port Memory Circuits - Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code. | 10-03-2013 |
20140104960 | Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits - Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data. | 04-17-2014 |
20140185364 | Methods And Apparatus For Designing And Constructing Multi-Port Memory Circuits - Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system. | 07-03-2014 |