Patent application number | Description | Published |
20090195948 | METHODS FOR MAKING A STARTING SUBSTRATE WAFER FOR SEMICONDUCTOR ENGINEERING HAVING WAFER THROUGH CONNECTIONS - The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections ( | 08-06-2009 |
20090302414 | TRENCH ISOLATION FOR REDUCED CROSS TALK - A starting substrate in the form of a semiconductor wafer ( | 12-10-2009 |
20100006536 | METHODS FOR MAKING MICRO NEEDLES AND APPLICATIONS THEREOF - The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry. | 01-14-2010 |
20100053922 | MICROPACKAGING METHOD AND DEVICES - A method of micro-packaging a component wherein at least a first and a second semi-conductor substrate are provided, one of which has electrical through connections (vias). A depression in either one of the substrates or in both is etched. A component is provided above vias and connected thereto. The substrates are joined to form a sealed package. A micro-packaged electronic or micromechanic device, including a thin-walled casing of a semi-conductor material having electrical through connections through the bottom of the casing is also disclosed. An electronic or micromechanic component is attached to the electrical through connections, and the package is hermetically sealed for maintaining a desired atmosphere, suitably vacuum inside the box. | 03-04-2010 |
20140063580 | VIA STRUCTURE AND METHOD THEREOF - A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro- mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided. | 03-06-2014 |
20140346657 | THIN FILM CAPPING - A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material. | 11-27-2014 |
20140378804 | INSULATION OF MICRO STRUCTURES - A method of providing a metal coating on a substrate ( | 12-25-2014 |
20150028479 | SEMICONDUCTOR DEVICES WITH CLOSE-PACKED VIA STRUCTURES HAVING IN-PLANE ROUTING AND METHOD OF MAKING SAME - The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided. | 01-29-2015 |
20150054136 | METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE - A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 μm. | 02-26-2015 |
20150076677 | CTE MATCHED INTERPOSER AND METHOD OF MAKING - The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1. | 03-19-2015 |