Patent application number | Description | Published |
20110138249 | Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code - An apparatus for detecting an error within a plurality of coded binary words coded by an error correction code includes a combiner connected town error detector. The combiner generates a combined binary word by combining a first coded binary word and a second coded binary word of the plurality of coded binary words, so that the determined combined binary word is a code word of the error correction code if the first coded binary word and the second coded binary word are code words of the error correction code, and so that the combined binary word is not a code word of the error correction code if the first coded binary word or the second coded binary word is not a code word of the error correction code. Further, the error detector may determine an error detection bit sequence indicating whether or not the combined binary word is a code word of the error correction code. | 06-09-2011 |
20110191658 | Method and Apparatus for Storing Data - When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data. | 08-04-2011 |
20120117448 | Apparatus and Method for Correcting at least one Bit Error within a Coded Bit Sequence - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 05-10-2012 |
20120144260 | Apparatus and Method for Detecting an Error Within a Coded Binary Word - An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word. | 06-07-2012 |
20130212441 | System and Method for Signature-Based Redundancy Comparison - A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison. | 08-15-2013 |
20130212452 | Apparatus and Method for Comparing Pairs of Binary Words - An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted. | 08-15-2013 |
20130346834 | APPARATUS AND METHOD FOR CORRECTING AT LEAST ONE BIT ERROR WITHIN A CODED BIT SEQUENCE - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 12-26-2013 |
20140075272 | DEVICE AND METHOD FOR TESTING A CIRCUIT TO BE TESTED - A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (T | 03-13-2014 |
20140173386 | Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error - A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′ | 06-19-2014 |