Patent application number | Description | Published |
20120032322 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate. | 02-09-2012 |
20120032343 | PACKAGE SUBSTRATE FOR BUMP ON TRACE INTERCONNECTION - A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example. | 02-09-2012 |
20120140427 | PRINTED CIRCUIT BOARD (PCB) ASSEMBLY WITH ADVANCED QUAD FLAT NO-LEAD (A-QFN) PACKAGE - A printed circuit board assembly (PCB) assembly is provided, including a printed circuit board (PCB) comprising a plurality of conductive pads and an advanced quad pack no-lead chip (a-QFN) package soldered to the printed circuit board. In one embodiment, the conductive pads have a first surface area and the QFN package includes a plurality of leads facing the conductive pads, having a second surface area, wherein a ratio between the second surface area and the first surface area is about 20% to 85% to ensure a physical connection between the PCB and the a-QFN package. | 06-07-2012 |
20130087911 | INTEGRATED CIRCUIT PACKAGE STRUCTURE - An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip. | 04-11-2013 |
20130140694 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate. | 06-06-2013 |
20130161810 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace. | 06-27-2013 |
20130168857 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs. | 07-04-2013 |
20130221536 | ENHANCED FLIP CHIP STRUCTURE USING COPPER COLUMN INTERCONNECT - A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only. | 08-29-2013 |
20140091481 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die. | 04-03-2014 |
20140127865 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed. | 05-08-2014 |
20140377913 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed. | 12-25-2014 |