Patent application number | Description | Published |
20090004573 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or more mask rules defining the minimum spacing between photomask patterns. The method further comprises determining the position of a first photomask pattern relative to an adjacent second photomask pattern, the first photomask pattern having a critical edge for defining a critical dimension of a first device structure and a non-critical edge for defining a non-critical dimension. The non-critical edge is attached to the critical edge so that the positioning of the non-critical edge will affect the length of the critical edge. The non-critical edge of the first photomask pattern is positioned a distance X from an edge of the second photomask pattern, wherein the distance X is chosen to be substantially the minimum spacing allowed by the mask rules. Embodiments directed to software modules for implementing the method and patterning processes employing the method are also disclosed. | 01-01-2009 |
20090087619 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method comprises receiving data describing a drawn pattern. An edge of the drawn pattern is identified that can be defined using a first photomask and a second photomask, and the first photomask is chosen for patterning the edge. Patterns are formed for the first photomask and the second photomask, wherein the first photomask pattern is formed to pattern the edge, and the second photomask pattern is formed to have a wing adjacent to the edge for protecting the edge from double patterning. A process for patterning an integrated circuit device is also disclosed. | 04-02-2009 |
20090087754 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning lithography process. The method comprises receiving data describing a drawn pattern. A first photomask pattern is formed for implementing a region of the drawn pattern on the substrate. A second photomask pattern is formed comprising one or more pattern features having longitudinal edges for implementing the region of the drawn pattern on the substrate, wherein at least 90% of all the longitudinal edges of the second photomask pattern that are positioned within the region are oriented in substantially the same direction. Both a system for forming the photomask patterns and a process for patterning a device using the photomask patterns are also disclosed. | 04-02-2009 |
20090125864 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database. | 05-14-2009 |
20090125865 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught. | 05-14-2009 |
20090125870 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database, the drawn pattern data describing device circuit features and dummy features. The dummy features have first target patterns. Mask pattern data is generated for the dummy features, wherein one or more of the dummy features have second target patterns that are different from the first target patterns. The mask pattern data is corrected for proximity effects. | 05-14-2009 |
20090125871 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present disclosure is directed a method for, preparing a photomask pattern. The method comprises receiving drawn pattern data from a design database. The drawn pattern data describes two or more adjacent feature ends that are positioned at different locations along a y-axis. A photomask pattern is formed for patterning the feature ends, wherein the photomask pattern will result in the feature ends being positioned at the same location along the y-axis. | 05-14-2009 |
20090128788 | SYSTEM AND METHOD FOR MAKING PHOTOMASKS - The present application is directed a method for determining the position of photomask patterns in a mask making process. The method comprises providing one or more mask rules defining the minimum spacing between photomask patterns. The method further comprises determining the position of a first photomask pattern relative to an adjacent second photomask pattern, the first photomask pattern having a critical edge for defining a critical dimension of a first device structure and a non-critical edge for defining a non-critical dimension. The non-critical edge is attached to the critical edge so that the positioning of the non-critical edge will affect the length of the critical edge. The non-critical edge of the first photomask pattern is positioned a distance X from an edge of the second photomask pattern, wherein the distance X is chosen to be substantially the minimum spacing allowed by the mask rules. Embodiments directed to software modules for implementing the method and patterning processes employing the method are also disclosed. | 05-21-2009 |
20090273100 | INTEGRATED CIRCUIT HAVING INTERLEAVED GRIDDED FEATURES, MASK SET AND METHOD FOR PRINTING | 11-05-2009 |
20100167537 | PARTITIONING FEATURES OF A SINGLE IC LAYER ONTO MULTIPLE PHOTOLITHOGRAPHIC MASKS - One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer. | 07-01-2010 |
20100308419 | SRAM Cell with T-Shaped Contact - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 12-09-2010 |
20110033785 | METHOD OF FABRICATING INTEGRATED CIRCUIT USING ALTERNATING PHASE-SHIFT MASK AND PHASE-SHIFT TRIM MASK - An integrated circuit is fabricated using photolithography by selectively exposing a photoresist layer to pattern a coarse line region of a wafer layer using a trim mask, and to pattern a fine line region of the wafer layer using an alternating phase-shift mask. The trim mask includes transparent, attenuated phase-shift and opaque regions. The phase-shifted attenuated light region patterns the coarse line region and the opaque region keeps light from exposing the fine line region. The alternating phase-shift mask patterns only the fine line region and includes one or more alternating phase-shift regions that each overlaps at least a portion of the opaque region but does not overlap the attenuated phase-shift region. The alternating phase-shift mask may be used to pattern the trim mask. | 02-10-2011 |
20110156168 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 06-30-2011 |
20110159684 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 06-30-2011 |
20110204452 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 08-25-2011 |
20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
20120102441 | MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS - A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site. | 04-26-2012 |
20120107729 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 05-03-2012 |
20120220133 | Integrated Circuit Having Interleaved Gridded Features, Mask Set, and Method for Printing - A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer. | 08-30-2012 |
20120228722 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 09-13-2012 |
20120258593 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 10-11-2012 |
20120264293 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than | 10-18-2012 |
20120264294 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 10-18-2012 |
20120286331 | INTEGRATED CIRCUITS AND PROCESSES FOR PROTECTION OF STANDARD CELL PERFORMANCE FROM CONTEXT EFFECTS - Integrated circuit ( | 11-15-2012 |
20130069081 | Layout Method To Minimize Context Effects and Die Area - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor. | 03-21-2013 |
20130244144 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 09-19-2013 |
20130246983 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 09-19-2013 |