Patent application number | Description | Published |
20080232158 | OPTIMIZED PHASE CHANGE WRITE METHOD - A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching. | 09-25-2008 |
20080258203 | STACKED SONOS MEMORY - An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell. | 10-23-2008 |
20080265239 | INTEGRATED CIRCUIT INCLUDING SPACER MATERIAL LAYER - An integrated circuit includes a first electrode and a dielectric material layer contacting a first portion of the first electrode. The integrated circuit includes a spacer material layer contacting a sidewall portion of the dielectric material layer and a second portion of the first electrode. The second portion is within the first portion. The integrated circuit includes resistivity changing material contacting the spacer material layer and a third portion of the first electrode. The third portion is within the second portion. The integrated circuit includes a second electrode contacting the resistivity changing material. | 10-30-2008 |
20080266932 | CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT - An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states. | 10-30-2008 |
20080272354 | PHASE CHANGE DIODE MEMORY - An integrated circuit having a memory includes a semiconductor line and a phase change element contacting the semiconductor line. The phase change element provides a storage location. A diode junction is formed at the interface between the semiconductor line and the phase change element. | 11-06-2008 |
20080273371 | MEMORY INCLUDING WRITE CIRCUIT FOR PROVIDING MULTIPLE RESET PULSES - An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first amplitude to the selected memory cell. | 11-06-2008 |
20080273378 | MULTI-LEVEL RESISTIVE MEMORY CELL USING DIFFERENT CRYSTALLIZATION SPEEDS - An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds. | 11-06-2008 |
20080296553 | INTEGRATED CIRCUIT HAVING CONTACT INCLUDING MATERIAL BETWEEN SIDEWALLS - An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit includes first material between the sidewalls of the contact. | 12-04-2008 |
20080303013 | INTEGRATED CIRCUIT INCLUDING SPACER DEFINED ELECTRODE - An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode. | 12-11-2008 |
20080303015 | MEMORY HAVING SHARED STORAGE MATERIAL - An integrated circuit includes a bit line and a plurality of access devices coupled to the bit line. The integrated circuit includes a plate of phase change material and a plurality of contacts. Each contact is coupled to an access device and contacting the plate of phase change material. A phase change element is formed at each intersection of a contact and the plate of phase change material. | 12-11-2008 |
20080304310 | MEMORY HAVING SHARED STORAGE MATERIAL - An integrated circuit includes a bit line, a plurality of access devices coupled to the bit line, and a plate of phase change material. The integrated circuit includes a plurality of phase change elements contacting the plate of phase change material and a plurality of first contacts. Each first contact is coupled between an access device and a phase change element. | 12-11-2008 |
20080304311 | INTEGRATED CIRCUIT INCLUDING LOGIC PORTION AND MEMORY PORTION - An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N. | 12-11-2008 |
20080315171 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a diode including a first polarity region and a second polarity region. The second polarity region contacts a bottom and sidewalls of the first polarity region. The integrated circuit includes a first electrode coupled to the diode, a second electrode, and resistivity changing material between the first electrode and the second electrode. | 12-25-2008 |
20080315172 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a vertical diode defined by crossed line lithography. | 12-25-2008 |
20080315173 | INTEGRATED CIRCUIT HAVING MULTILAYER ELECTRODE - An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode. | 12-25-2008 |
20080315359 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material. | 12-25-2008 |
20080316793 | INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE - An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode. | 12-25-2008 |
20080316794 | INTEGRATED CIRCUIT HAVING MULTILAYER ELECTRODE - An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material. | 12-25-2008 |
20080316802 | MEMORY DEVICE HAVING DRIFT COMPENSATED READ OPERATION AND ASSOCIATED METHOD - A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels. | 12-25-2008 |
20090001341 | Phase Change Memory with Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 01-01-2009 |
20090003032 | INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL HAVING A PLANARIZED SURFACE - An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material. | 01-01-2009 |
20090003034 | MULTIPLE WRITE CONFIGURATIONS FOR A MEMORY CELL - One embodiment of the present invention relates to a method of programming an array of memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, each of which can write at least two data states to the memory cells of the array. Other embodiments are also disclosed. | 01-01-2009 |
20090003035 | CONDITIONING OPERATIONS FOR MEMORY CELLS - One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed. | 01-01-2009 |
20090003044 | PROGRAM METHOD WITH LOCALLY OPTIMIZED WRITE PARAMETERS - A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. | 01-01-2009 |
20090014704 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 01-15-2009 |
20090020738 | INTEGRATED CIRCUIT INCLUDING FORCE-FILLED RESISTIVITY CHANGING MATERIAL - An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode. | 01-22-2009 |
20090176354 | METHOD FOR FABRICATION OF SINGLE CRYSTAL DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device. | 07-09-2009 |
20090289242 | Phase Change Memory With Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 11-26-2009 |
20100193763 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 08-05-2010 |
20100321990 | Memory Including Vertical Bipolar Select Device and Resistive Memory Element - A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base. | 12-23-2010 |
20100323493 | Method for Fabricating an Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface - An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material. | 12-23-2010 |
20110198557 | METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si. | 08-18-2011 |