Patent application number | Description | Published |
20080277691 | Production of a Transistor Gate on a Multibranch Channel Structure and Means for Isolating This Gate From the Source and Drain Regions - A method for fabricating a microelectronic device including a support, an etched stack of thin layers including at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, plural semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or plural transistor channels. A gate surrounds the bars and is located between the first block and the second block, the gate being in contact with a first and second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via the insulating spacers. | 11-13-2008 |
20090085119 | DOUBLE-GATE TRANSISTOR STRUCTURE EQUIPPED WITH A MULTI-BRANCH CHANNEL - Double gate transistor microelectronic device comprising:
| 04-02-2009 |
20090124050 | METHOD OF MANUFACTURING NANOWIRES PARALLEL TO THE SUPPORTING SUBSTRATE - A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method comprising:
| 05-14-2009 |
20090203203 | METHOD FOR THE FABRICATION OF A TRANSISTOR GATE THAT INCLUDES THE BREAKDOWN OF A PRECURSOR MATERIAL INTO AT LEAST ONE METALLIC MATERIAL, USING AT LEAST ONE - A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type. | 08-13-2009 |
20090246946 | METHOD OF FABRICATING A MICROELECTRONIC STRUCTURE OF A SEMICONDUCTOR ON INSULATOR TYPE WITH DIFFERENT PATTERNS - A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged. | 10-01-2009 |
20100219489 | NANOWIRE SENSOR DEVICE - The invention concerns a sensor device, of nanowire type, comprising at least one nanowire comprising a first conductive region ( | 09-02-2010 |
20100264496 | SRAM MEMORY CELL PROVIDED WITH TRANSISTORS HAVING A VERTICAL MULTICHANNEL STRUCTURE - A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate. | 10-21-2010 |
20100273317 | METHOD OF GROWING, ON A DIELETRIC MATERIAL, NANOWIRES MADE OF SEMI-CONDUCTOR MATERIALS CONNECTING TWO ELECTRODES - Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material. | 10-28-2010 |
20110067985 | CONCEPTION OF AN ELECTRO-MECHANICAL COMPONENT FOR A MICRO- OR NANO-SYSTEM EQUIPPED WITH A BAR FORMING AN AXIS OF ROTATION OF THE COMPONENT AND COATED IN GRAPHENE - Method of fabricating an electro-mechanical microsystem provided with at least one fixed part comprising a bar, and at least one mobile part in rotation around at least one portion of said bar, the method comprising the steps of:
| 03-24-2011 |
20110124161 | STRUCTURE AND METHOD FOR FABRICATING A MICROELECTRONIC DEVICE PROVIDED WITH ONE OR MORE QUANTUM WIRES ABLE TO FORM ONE OR MORE TRANSISTOR CHANNELS - The disclosure concerns a microelectronic device provided with one or more <>, able to form one or more transistor channels, and optimized in terms of arrangement, shape or/and composition. The invention also uses a method for fabricating said device, comprising the steps of: the forming, in one or more thin layers resting on a support, of a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, and of a structure connecting the first block to the second block, and the forming, on the surface of the structure, of wires connecting a first region of the first block with another region of the second block which faces the first region. | 05-26-2011 |
20110169067 | STRUCTURE AND PRODUCTION PROCESS OF A MICROELECTRONIC 3D MEMORY DEVICE OF FLASH NAND TYPE - A microelectronic flash memory device including a plurality of memory cells including transistors fitted with a matrix of channels connecting a block of common source to a second block on which bit lines rest, the transistors also being formed by a plurality of gates including at least one gate material, including a first selection gate coating the channels, a plurality of control gates coating the channels, a plurality of second selection gates each coating the channels of the same row and the matricial arrangement, at least one or more of the gates based on superposition of layers including at least one first layer of dielectrical material, at least one charge store zone, and at least one second layer of dielectrical material. | 07-14-2011 |
20110281412 | PRODUCTION OF A TRANSISTOR GATE ON A MULTIBRANCH CHANNEL STRUCTURE AND MEANS FOR ISOLATING THIS GATE FROM THE SOURCE AND DRAIN REGIONS - A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers. | 11-17-2011 |
20120134206 | MULTILEVEL MEMORY DEVICE - A memory device comprising:
| 05-31-2012 |
20130144542 | ANALYSIS DEVICE INCLUDING A MEMS AND/OR NEMS NETWORK - A device for analyzing a fluid, including a layer including a plurality of sensors of MEMS and/or NEMS type, a layer including a mechanism controlling the sensor and for processing information transmitted by the sensors, the control and processing mechanism being electrically connected to the detectors, and a layer positioned on the layer including the sensors on a side of a face including the sensors including a mechanism spatially and temporally distributing the fluid on the sensors. | 06-06-2013 |
20130187276 | MICROELECTRONIC DEVICE HAVING METAL INTERCONNECTION LEVELS CONNECTED BY PROGRAMMABLE VIAS - A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element. | 07-25-2013 |
20130203248 | INTEGRATED CIRCUIT HAVING A JUNCTIONLESS DEPLETION-MODE FET DEVICE - A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer. | 08-08-2013 |