Patent application number | Description | Published |
20130207168 | PHOTODIODE EMPLOYING SURFACE GRATING TO ENHANCE SENSITIVITY - A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a surface grating of periodic field oxide in a periodic configuration and/or gate structures in a periodic configuration is formed. The field oxide may be formed using an STI process or a LOCOS process. A semiconductor device with a surface grating including both field oxide and gate structures has the gate structures over the semiconductor substrate, between the field oxide. The surface grating has a pitch length up to 3 microns. The surface grating covers at least half of the photodiode. | 08-15-2013 |
20130207210 | LOW-CAPACITANCE PHOTODIODE UTILIZING VERTICAL CARRIER CONFINEMENT - A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region. | 08-15-2013 |
20130207211 | WAVELENGTH SENSITIVE PHOTODIODE EMPLOYING SHORTED JUNCTION - A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit. | 08-15-2013 |
20130207746 | RF MIXER FILTER MEMS RESONATOR ARRAY - A MEMS mixer filter including an array of a multiplicity of resonator elements with conductive outer surfaces in a coplanar rectangularly tiled array, and two sets of DC bias lines in which alternating resonator elements in each row and column are connected to one or the other sets of bias lines so that laterally adjacent resonators may be biased to a DC potential. The resonator elements are uniform in size and shape. Lateral dimensions of the resonator elements are between 5 and 50 microns. The resonator elements are between 100 nanometers and 100 microns thick, and adjacent resonator elements are separated by a gap between 100 and 500 nanometers. A process of forming the MEMS mixer filter. | 08-15-2013 |
20130214159 | INFRARED LIGHT TRANSMISSIVITY FOR A MEMBRANE SENSOR - In conventional membrane infrared (IR) sensors, little to no attention has been paid toward transmissivity of IR near metal traces. Here, because the substrate of an integrated circuit carrying the sensor is used as a visible light filter, reflection of IR radiation back into the substrate can affect the operation and reliability of the IR sensor. As a result, an arrangement is provided that reduces the area occupied by metal lines by reducing the pitch and compacting the routing so as to reduce the effects from the reflection of IR radiation by metal traces. | 08-22-2013 |
20130214289 | Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor - A protective cap is formed on the metal gate of a MOS transistor to protect the metal gate during an etch that forms a source contact opening and a drain contact opening. The protective cap also electrically isolates the source metal contact and the drain metal contact from the metal gate. | 08-22-2013 |
20130214616 | TRANSMISSION LINE PULSING - A circuit and method for electrostatic discharge testing using transmission line pulsing. A plurality of transmission line networks may be connected to a device under test, and each transmission line network may have different connected terminations. Switches may be used to select which transmission line networks are connected to the device under test, and which terminations, if any, are connected to transmission line networks. | 08-22-2013 |
20130214700 | LED CONTROL SYSTEM - One embodiment includes a light-emitting diode (LED) control system. The system includes an LED driver system configured to regulate a control voltage based on a substantially constant reference current and a feedback voltage at a feedback node. The system also includes a digital current source system comprising a plurality of unit current sources that are each coupled to an LED. The plurality of unit current sources can be selectively activated to each provide a given unit current through the LED and to each provide the feedback voltage as an interpolative feedback to the feedback node based on the unit current. The system further includes a current magnitude controller configured to selectively activate the plurality of unit current sources in response to a current magnitude signal. | 08-22-2013 |
20130214755 | STABILIZATION SYSTEM AND METHOD FOR INPUT OSCILLATION - A system and method for controlling power supply input filter oscillations is provided. The method includes utilizing a converter power circuit to generate a positive input resistance to counteract input filter oscillations, which are generated in response to normal converter negative input impedance and current-mode control operation. A controller controls the converter power circuit to generate the positive resistance utilizing a first input corresponding to the voltage applied to the converter input. A second input disables the converter power circuit based on completion of output capacitor charge, the first and second inputs being different. | 08-22-2013 |
20130217216 | Unguarded Schottky Barrier Diodes with Dielectric Underetch at Silicide Interface - One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed. | 08-22-2013 |
20130217399 | PARTIAL CHANNEL MAPPING FOR FAST CONNECTION SETUP IN LOW ENERGY WIRELESS NETWORKS - A system comprising a controller, a scanner, and a transceiver. The controller is configured to identify a number of channels in which a beacon signal may be wirelessly transmitted. The number of channels is less than a total number of channels available for receiving transmissions. The scanner is configured to scan each of the number of channels for a first beacon signal. The transceiver is configured to receive the first beacon signal from one of the number of channels. | 08-22-2013 |
20130219195 | DEVICES AND METHODS FOR TRANSMITTING POWER OVER AN ETHERNET LINE - Circuits and methods for providing power from power sourcing equipment to a powered device using an ethernet cable are disclosed herein. An embodiment of the method includes detecting a resistance value in the powered device, wherein the resistance value determines whether the powered device can receive power. A first class event is performed to determine the class of the powered device. A second class event is then performed to determine the class of the powered device. Power is transmitted on all four pairs of the ethernet cable simultaneously when the first and second class events indicate that the class of the powered device conforms to a class that can receive power from the power sourcing equipment on all four pairs. | 08-22-2013 |
20130219239 | DIE STACK TEST ARCHITECTURE AND METHOD - A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die. | 08-22-2013 |
20130221451 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 08-29-2013 |
20130221526 | System in Package and Method for Manufacturing The Same - A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step. | 08-29-2013 |
20130222181 | ENHANCING SEARCH CAPACITY OF GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) RECEIVERS - Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search. | 08-29-2013 |
20130222403 | SPATIAL AND TEMPORAL PULSE WIDTH MODULATION METHOD FOR IMAGE DISPLAY - A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the positions of a first subgroup of micromirrors of a reset group are set based on a first portion of a first bitplane and the positions of a second subgroup of micromirrors of the same reset group are set based on a first portion of a second bitplane. Then, in a second reset operation, the positions of the first subgroup are set based on a second portion of the second bitplane and the positions of the second subgroup are set based on a second portion of a first bitplane. In one example, subsets of alternating rows of micromirrors of the same reset group are successively set according to alternating data corresponding to different ones of first and second bitplanes. | 08-29-2013 |
20130223457 | Multi-Length Cyclic Prefix for OFDM Transmission in PLC Channels - Embodiments of the invention provide multiple cyclic prefix lengths for either both the data-payload and frame control header or only the data payload. Frame control header (FCH) and data symbols have an associated cyclic prefix. A table is transmitted in the FCH symbols, which includes a cyclic prefix field to identify the cyclic prefix length used in the data payload. A receiver may know the cyclic prefix length used in the FCH symbols in one embodiment. In other embodiments, the receiver does not know the FCH cyclic prefix length and, therefore, attempts to decode the FCH symbols using different possible cyclic prefix lengths until the FCH symbols are successfully decoded. | 08-29-2013 |
20130223542 | Sample Adaptive Offset (SAO) Parameter Signaling - Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. More specifically, techniques are provided that allow SAO information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. These techniques reduce the need to signal SAO information separately for each color component. | 08-29-2013 |
20130224940 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 08-29-2013 |
20130227363 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 08-29-2013 |
20130227364 | DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM - A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed. | 08-29-2013 |
20130227365 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 08-29-2013 |
20130227377 | RECEIVERS, CIRCUITS, AND METHODS TO IMPROVE GNSS TIME-TO-FIX AND OTHER PERFORMANCES - An electronic circuit ( | 08-29-2013 |
20130227513 | GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS - In a first embodiment a TAP | 08-29-2013 |
20130285944 | PROGRAMMABLE RESISTIVE MULTI-TOUCH DETECTIONS AND REGIONALIZED RESISTIVE MULTI-TOUCH SENSING - An apparatus comprises touch screen interface and signal processing circuit. Within touch screen interface, there are switching circuits configured to be coupled to at least one of a plurality of column electrodes, and there are touch detection circuits configured to be coupled to at least one of a plurality of row electrodes. The signal processing circuit is coupled to each switching circuit and each touch detection circuit so as to be able to selectively activate the plurality of switching circuits and touch detection circuits to identify a zone for a touch event. The signal processing circuit determines first, second, third, and fourth resistances for the zone for the touch event and determines a set of coordinates and pressure for the touch event from its first, second, third, and fourth resistances. A zone controller, wherein the first and second rows are previously enabled, but a third row is not enabled. | 10-31-2013 |
20130286361 | SELECTABLE THROW RATIO IMAGE PROJECTION DEVICE - A portable image projection device has a housing with first and second members pivotable between device folded and unfolded positions. First lens optics mounted within the first member are configured for projecting light modulated by a spatial light modulator along an optical axis through a first aperture with a first throw ratio with the device in the folded position. A second lens optics element movably mounted within the first member is configured for selective movement between positions of non-intersection and intersection with the optical axis. The second lens optics element is configured for cooperating with at least part of the first lens optics for projecting the light modulated by the spatial light modulator along the optical axis through a second aperture with a second throw ratio less than the first throw ratio with the device in the unfolded position. | 10-31-2013 |
20130287044 | MAC EXTENSIONS FOR SMART ANTENNA SUPPORT - Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively. | 10-31-2013 |
20130290765 | CHARGING A PROVIDER/CONSUMER WITH A DEAD BATTERY VIA USB POWER DELIVERY - A method and apparatus are provided. The VBUS conductor is checked to determine whether the voltage on the VBUS conductor is greater than a vSafe0V voltage within a dead battery detect time interval, and the device policy manager is instructed to apply a vSafeDB voltage to the VBUS conductor if the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a bit stream detect timer interval. If the bit stream is not detected within the bit stream detect timer interval, then the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager is instructed to apply a vSafe5V voltage to the VBUS conductor if the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. If the bit stream has stopped within the device ready timer interval, then the policy engine sends capabilities as a source port. | 10-31-2013 |
20130308222 | DISK-DRIVE PULSE DURATION CONTROL SYSTEM - One embodiment includes a pulse duration control system for a magnetic disk-drive system. A rise delay system generates first control voltages in response to a write data input signal changing between a first state and a second state. A fall delay system generates second control voltages in response to the write data input signal changing between the first and second states. A comparator system generates a rising-edge overshoot signal and a falling-edge overshoot signal based on a comparison of the first and second control voltages. The rising-edge overshoot signal can set a duration of a positive overshoot current pulse for a write current at a transition of the write data input signal from the first state to the second state, and the falling-edge overshoot signal can set a duration of a negative overshoot current pulse for the write current at a transition from the second state to the first state. | 11-21-2013 |
20130308696 | Method and Apparatus for Sample Adaptive Offset Without Sign Coding - A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset. | 11-21-2013 |
20130332103 | CELL BASED TEMPERATURE MONITORING - A system and method for measuring a temperature in at least one energy storage unit. They system includes at least one temperature sensor thermally coupled to the at least one energy storage unit, and a battery management controller in communication with the at least one temperature sensor. The battery management controller is configured to process a temperature of the at least one energy storage unit to obtain an internal temperature in the at least one energy storage unit. | 12-12-2013 |
20140029583 | Systems and Methods for Time Optimization for Silencing Wireless Devices in Coexistence Networks - Embodiments provide systems and methods to optimize the time when to transmit a silencing frame, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A device comprises at least two dissimilar network technology subsystems, at least one subsystem of which is lower priority than at least another of the dissimilar subsystems. In some embodiments, a device is able to transmit a silencing frame during a transmission window within a lower priority technology network interval. In other embodiments, a device calculates a transmission window, the transmission window to occur within a lower priority technology network interval, and transmits a silencing frame during the transmission window. In further embodiments, a device is able to calculate a transmission window to occur during a lower priority technology network interval, and transmit a silencing frame during the calculated transmission window. | 01-30-2014 |
20140035057 | INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 02-06-2014 |
20140063312 | METHODS FOR COMBINING CAMERA AND PROJECTOR FUNCTIONS IN A SINGLE DEVICE - Described are handheld devices with combined image capture and image projection functions. One embodiment includes modulating and capturing a light beam along the same optic path. In another embodiment, the optical components are operable to switch between projection and capture modes. In yet another embodiment, the optical components may be formed on the same semiconductor substrate thereby increasing functionality. | 03-06-2014 |
20140086155 | METHOD AND APPARATUS FOR CSI FEEDBACK IN CoMP (COORDINATED MULTI-POINT) SYSTEMS - A method and apparatus for coordinating a multi-point wireless transmission between a plurality of geographically separated transmission points and at least one user equipment. | 03-27-2014 |
20140167295 | COATINGS FOR RELATIVELY MOVABLE SURFACES - A device comprises a MEMS component comprising at least one surface and a coating disposed on at least a portion of the surface. The coating comprises a compound of the formula M(C | 06-19-2014 |
20140173162 | Command Queue for Communications Bus - Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module. | 06-19-2014 |
20140198977 | Enhancement of Stereo Depth Maps - A method for computation of a depth map for corresponding left and right two dimensional (2D) images of a stereo image is provided that includes determining a disparity range based on a disparity of at least one object in a scene of the left and right 2D images, performing color matching of the left and right 2D images, performing contrast and brightness matching of the left and right 2D images, and computing a disparity image for the left and right 2D images after the color matching and the contrast and brightness matching are performed, wherein the disparity range is used for correspondence matching of the left and right 2D images. | 07-17-2014 |
20140239979 | CAPACITIVE MEMS SENSOR DEVICES - A packaged capacitive MEMS sensor device includes at least one capacitive MEMS sensor element with at least one capacitive MEMS sensor cell including a first substrate having a thick and a thin dielectric region. A second substrate with a membrane layer is bonded to the thick dielectric region and over the thin dielectric region to provide a MEMS cavity. The membrane layer provides a fixed electrode and a released MEMS electrode over the MEMS cavity. A first through-substrate via (TSV) extends through a top side of the MEMS electrode and a second TSV through a top side of the fixed electrode. A metal cap is on top of the first TSV and second TSV. A third substrate including an inner cavity and outer protruding portions framing the inner cavity is bonded to the thick dielectric regions. The third substrate together with the first substrate seals the MEMS electrode. | 08-28-2014 |
20140240062 | Dielectric Waveguide with Deformable Interface Surface - A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG | 08-28-2014 |
20140240187 | Dielectric Waveguide with Non-planar Interface Surface - A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end. | 08-28-2014 |
20140241549 | Robust Estimation of Sound Source Localization - A method for sound source localization in a digital system having at least two audio capture devices is provided that includes receiving audio signals from the two audio capture devices, computing a signal-to-noise ratio (SNR) for each frequency band of a plurality of frequency bands in a processing frame of the audio signals, determining a frequency band weight for each frequency band of the plurality of frequency bands based on the SNR computed for the frequency band, computing an estimated time delay of arrival (TDOA) of sound for the processing frame using the frequency band weights, and converting the estimated TDOA to an angle representing sound direction. | 08-28-2014 |
20140266311 | SAMPLED REFERENCE SUPPLY VOLTAGE SUPERVISOR - A power supervisor circuit is provided. The circuit includes a first sample circuit that periodically samples a first reference voltage derived from a high output rail of a voltage source and generates a first sampled output voltage. The circuit includes second sample circuit that periodically samples a second reference voltage associated with a low output rail of the voltage source and generates a second sampled output voltage. A voltage supervisor in the circuit generates a trip point signal when a combination of the first and second sampled output voltage crosses a predetermined threshold indicating that the voltage source output voltage has fallen below a desired output voltage. | 09-18-2014 |
20140285277 | Dielectric Waveguide Manufactured Using Printed Circuit Board Technology - A dielectric waveguide may be manufactured by forming a set of parallel channels in a planar sheet that has a lower dielectric constant value. The set of channels is then filled with a material having a higher dielectric constant value. The planar sheet is sliced into a plurality of strips that each contain one or more of the channels. | 09-25-2014 |
20140285281 | Coupler to Launch Electromagnetic Signal from Microstrip to Dielectric Waveguide - A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line. | 09-25-2014 |
20140285289 | Horn Antenna for Launching Electromagnetic Signal from Microstrip to Dielectric Waveguide - A horn antenna is formed within a multilayer substrate and has a generally trapezoidal shaped top plate and bottom plate formed in different layers of the multilayer substrate. A set of densely spaced vias form two sidewalls of the horn antenna by coupling adjacent edges of the top plate and the bottom plate. The horn antenna has a narrow input end and a wider flare end. A microstrip line is coupled to the top plate and a ground plane element is coupled to the bottom plate at the input end of the horn antenna. | 09-25-2014 |
20140285290 | Dielectric Waveguide Combined with Electrical Cable - A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding. | 09-25-2014 |
20140285291 | Dielectric Waveguide with Multiple Channels - A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant. | 09-25-2014 |
20140285292 | Dielectric Waveguide with Corner Shielding - A dielectric wave guide (DWG) has a longitudinal dielectric core member. The core member has a first dielectric constant value. A cladding surrounds the dielectric core member and has a second dielectric constant value that is lower than the first dielectric constant. A portion of the DWG is configured as a corner having a radius. A conductive layer formed on an outer radius of the corner. | 09-25-2014 |
20140285293 | Dielectric Waveguide with RJ45 Connector - A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding surrounding the dielectric core member that has a second dielectric constant value that is lower than the first dielectric constant. An RJ45 compatible connector is attached to a mating end of the DWG. The RJ45 connector is configured to retain a complimentary coupling mechanism on a mating end of a second DWG. | 09-25-2014 |
20140287701 | Integrated Circuit with Dipole Antenna Interface for Dielectric Waveguide - An electronic device has a multilayer substrate that has an interface surface configured for interfacing to a dielectric waveguide. A conductive layer on the substrate is etched to form a dipole antenna disposed adjacent the interface surface to provide coupling to the dielectric waveguide. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. | 09-25-2014 |
20140287702 | Dielectric Waveguide with Director Elements - A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an interface surface configured for interfacing to the mating end of the DWG. A conductive layer is etched to form a dipole antenna disposed adjacent the interface surface. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. A set of director elements is embedded in the mating end of the DWG. Specific spacing is maintained between the dipole antenna and the set of director elements. | 09-25-2014 |
20140287703 | Integrated Circuit with Antenna for Dielectric Waveguide - A system includes an integrated circuit that has a substrate with a top surface and a bottom surface. Semiconductor circuitry is including a radio frequency (RF) amplifier configured to produce an RF signal or an RF receiver configured to receive an RF signal is formed on the top surface of the substrate. A through-substrate via is coupled to an output of the RF amplifier. A metalized antenna formed on the bottom surface of the substrate is coupled to the through-substrate via. The metalized antenna is configured to launch an electromagnet wave representative of the RF signal into a dielectric waveguide (DWG) when the DWG is coupled to the bottom side of the substrate. | 09-25-2014 |