Patent application number | Description | Published |
20080223336 | ENGINE CONTROL SYSTEM - An engine control device includes a governor lever, a centrifugal governor, a control lever operated to oscillate between a low-speed position and a high-speed position, and a governor spring expandedly provided between the control lever and the governor lever. An automatic choke device is connected to a choke valve of a carburetor. A play is provided between the governor lever and the governor spring. The play holds the governor spring in a free state during rotation of the control lever from the low-speed position to the high-speed position by a predetermined angle. A subsidiary spring is provided between a fixed structure and the governor lever so as to constantly urge the governor lever in a direction to open the throttle valve. A spring constant of the subsidiary spring is smaller than that of the governor spring. Thus, there is provided the engine control system with the automatic choke device, which can meticulously control an air/fuel ratio from start of an engine to under-load operation of the engine in accordance with increase and decrease in temperature of the engine. | 09-18-2008 |
20110056463 | CARBURETOR CONTROL SYSTEM - A carburetor control system includes: a governor device that is coupled to a throttle lever, opens a throttle valve when an operation of an engine is stopped, and opens or closes the throttle valve in accordance with a rotational number of the engine when the engine is in operation; a choke return spring urging a choke lever in a direction to close a choke valve; and an automatic choke device opening the choke valve in accordance with an increase in temperature of the engine. In the carburetor control system, the throttle lever is provided with a drive arm pivoting the choke lever, during a cold operation of the engine, to a position where the choke valve is at an intermediate degree of opening in operative connection with the throttle lever being pivoted by the governor device to a position where the throttle valve is at a degree of opening for idling or a position in a vicinity thereof. Accordingly, it is possible to mechanically open the choke valve to a predetermined intermediate degree of opening, when the engine is in a cold idling state, in operative connection with the throttle valve, so as to be capable of ensuring a fuel-efficient and stable idling state. | 03-10-2011 |
20120152194 | VARIABLE VALVE OPERATING DEVICE FOR INTERNAL COMBUSTION ENGINE - In a variable valve operating device for an internal combustion engine, which is capable of changing operation characteristics of an engine valve in accordance with a change in rotation speed of a camshaft, a high-speed cam ( | 06-21-2012 |
20120161341 | AUTOMATIC CHOKE APPARATUS FOR CARBURETOR - An automatic choke apparatus for a carburetor includes an electric actuator, a choke valve opening/closing mechanism configured to open and close a choke valve by being driven by a power exerted by the electric actuator, and a controller configured to control operation of the electric actuator. The controller, to which a battery supplies electric power, operates the electric actuator and the choke valve opening/closing mechanism in order that, when the engine is stopped, the choke valve is set in a semi-opened position and, when the engine starts to be cranked, the choke valve is set in a fully-closed position. Accordingly, it is possible to prevent the choke valve from freezing up in the fully-closed state in a case where the engine is stopped under an extremely low temperature environment. | 06-28-2012 |
20140299095 | CONTROL APPARATUS FOR GENERAL-PURPOSE INTERNAL COMBUSTION ENGINE - In a control apparatus for a general-purpose internal combustion engine including a generator as a power supply, the generator includes a main generator coil supplying power to the stepping motor, and an auxiliary generator coil supplying power to an ignition device of the engine. The apparatus includes ignition timing controller for, when starting the engine by a manual starter, detecting that an engine speed reaches or exceeds a predetermined engine speed not exceeding a connecting rotation speed of a centrifugal clutch to retard an ignition timing of the engine, thereby suppressing increase in the engine speed to less than the connecting rotation speed, and for restoring the ignition timing to its normal timing after a predetermined time elapses from start of retarding the ignition timing. Accordingly, it suppresses overshooting of an engine speed above the connecting rotation speed even if a delay occurs in closing a throttle valve by a delay in activating the motor. | 10-09-2014 |
Patent application number | Description | Published |
20100124090 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - To provide data lines connected via column switches to a plurality of sense amplifiers and an input/output circuit that, in response to a write request, supplies pre-write data through the data line to selected phase change memory cells and then write data through the data line to the selected phase change memory cells. Thus, a pre-write operation and an actual write operation according to the write data can be performed at high speed. Because only the memory cells selected by a column address are subject to write, consumption power is reduced and lives of the memory cells are not shortened. | 05-20-2010 |
20100124141 | SEMICONDUCTOR MEMORY DEVICE OF DUAL-PORT TYPE - To provide a plurality of DRAM cells, a plurality of sense amplifiers connected to corresponding bit line pairs, a first column switch and a second column switch assigned to each of the sense amplifiers, data lines connected via the column switches to the sense amplifiers, a first port PORT | 05-20-2010 |
20100125774 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained. | 05-20-2010 |
20100182857 | TESTER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An apparatus testing a semiconductor device may include, but is not limited to, a first strobe signal generating circuit and a detecting circuit. The first strobe signal generating circuit generates a first strobe signal in response to a reference clock supplied from the semiconductor device. The detecting circuit detects a data signal, supplied from the semiconductor device, based on the first strobe signal. | 07-22-2010 |
20110292710 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR - A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially into the input node, on the basis of a setting signal, the plurality of input addresses including the first and second addresses, wherein the first control circuit being configured to set an input address as the first address based on the setting signal, and the first control circuit further being configured to set an input address as the second address on the basis of the setting signal when the first and second addresses are different each other in a predetermined portion of bits after the first address is set to the first ROM. | 12-01-2011 |
20110292752 | SEMICONDUCTOR MEMORY DEVICE HAVING FUSE ELEMENTS PROGRAMMED BY IRRADIATION WITH LASER BEAM - A relief-address control unit of a semiconductor memory device includes a fuse storage unit and a relief circuit. The fuse storage unit includes a plurality of fuse elements that are made nonconductive by irradiation with a laser beam, and a protective film with an opening directly above the fuse elements to facilitate the laser beam to pass through. The relief circuit specifies a relieved address based on a nonconductive state of the fuse elements. The opening is in a unified form along a long-side direction of the fuse storage unit. Further, the relief circuit is arranged adjacent to a short-side end of the fuse storage unit. | 12-01-2011 |
20130132797 | CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained. | 05-23-2013 |
20130162302 | SEMICONDUCTOR DEVICE HAVING DATA OUTPUT CIRCUIT IN WHICH SLEW RATE THEREOF IS ADJUSTABLE - Disclosed herein is a device that includes: a first circuit configured to operate on a first power voltage to produce a first set of slew rate control signals; a second circuit configured to operate on a second power voltage to produce a second set of slew rate control signals in response to the first set of slew rate control signals; and a third circuit configured to operate on the second power voltage to produce a signal at a rate that is controllable in response to the second set of slew rate control signals. | 06-27-2013 |
20130342238 | SEMICONDUCTOR DEVICE INCLUDING TRI-STATE CIRCUIT - Disclosed herein is a device that includes first and second logic circuits driving first and second output nodes, respectively. The first logic circuit includes first and second transistors that are coupled in series between the first output node and a power line, in which the first transistor is controlled to change between a conductive state and a non-conductive state and the second transistor is controlled to keep a conductive state. The second gate circuit includes third and fourth transistors that are coupled in series between the second output node and the power line, in which each of the third and fourth transistors is controlled to change between a conductive state and a non-conductive state. | 12-26-2013 |
20150063041 | SEMICONDUCTOR DEVICE - A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the data output terminal, and a calibration circuit to output an n-bit first code signal for controlling each of the n first transistors. In some embodiments, the calibration circuit includes a first counter circuit to output a k-bit second code signal (k is a natural number less than n), and a first code conversion circuit to convert the k-bit second code signal to the n-bit first code signal. Additional apparatus, systems, and methods are disclosed. | 03-05-2015 |