Patent application number | Description | Published |
20080297199 | ADJUSTABLE DRIVE STRENGTH APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die device and that provides the state of all of the dice at a common output. Such a multi-die device can comprise two or more dice in a multi-die package, wherein each of said dice has a first drive parameter when indicating a first state and a second drive parameter when indicating a second state. When the first drive parameter of the two or more dice is at a value such that when one or more of said two or more dice is in the first state, said common output can indicate that all of the dice in the multi-die device are in the first state. | 12-04-2008 |
20120233433 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR MEMORY INITIALIZATION - Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices. | 09-13-2012 |
20120311297 | LOGICAL UNIT ADDRESS ASSIGNMENT - Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed. | 12-06-2012 |
20130031326 | DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION - The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry. | 01-31-2013 |
20130099818 | METHODS AND APPARATUSES INCLUDING AN ADJUSTABLE TERMINATION IMPEDANCE RATIO - Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions of a termination circuit coupled to a node are selectively programmed to adjust an impedance of the termination circuit to adjust the centerline voltage of the data signal driven to the node. One such apparatus includes pull-up impedances and pull-down impedances that can be programmed to adjust the centerline voltage of the data signal. Additional embodiments are also described. | 04-25-2013 |
20130103890 | CALIBRATING MEMORY - Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window. | 04-25-2013 |
20140050030 | METHODS AND APPARATUSES INCLUDING A VARIABLE TERMINATION IMPEDANCE RATIO - Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described. | 02-20-2014 |
20150052317 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR MEMORY INITIALIZATION - Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices. | 02-19-2015 |