Patent application number | Description | Published |
20120316794 | METHOD AND A SYSTEM FOR MONITORING A PHYSIOLOGICAL PARAMETER OF A SUBJECT - Embodiments provide a method which includes transmitting, by a receiving device (RD), a request message which includes a receiving device identification number (RDIN); receiving, by the RD, a registration message including a measuring device identification number (MDIN) from a measuring device (MD); registering, by the RD, the MD by means of the MDIN if the registration message from the MD includes the RDIN; receiving, by the RD, one or more data messages from the MD, each data message including the MDIN and a physiological parameter; and processing the physiological parameter in each data message, by the RD, if the MD has been registered by the RD. The range of the transmission of the request message between the RD and the MD is shorter than the range of the transmission of each data message between the MD and the RD, and/or the range of the transmission of the registration message between the MD and the RD is shorter than the range of the transmission of each data message between the MD and the RD. Embodiments also provide a corresponding monitoring system. | 12-13-2012 |
20150137948 | TAGS, METHODS OF USING TAGS, SYSTEMS, AND METHODS OF USING SYSTEMS - Various embodiments relate to tags, methods of using tags, systems, and methods of using systems. Various embodiments may be suitable for identifying a human or an animal. Various embodiments may provide mother-infant matching and cot-infant matching for both single and multiple births; monitoring of the location, movement, and status of the tags; detection of tampering and unauthorized removal of infant tags; and organizing of tags. | 05-21-2015 |
Patent application number | Description | Published |
20080315317 | SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS - A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor. | 12-25-2008 |
20090026549 | METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS - An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors. | 01-29-2009 |
20090085122 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 04-02-2009 |
20090218636 | INTEGRATED CIRCUIT SYSTEM FOR SUPPRESSING SHORT CHANNEL EFFECTS - An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening. | 09-03-2009 |
20090315115 | Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement - A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance. | 12-24-2009 |
20100059831 | Spacer-less Low-K Dielectric Processes - A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator. | 03-11-2010 |
20100078687 | Method for Transistor Fabrication with Optimized Performance - A semiconductor process and apparatus includes forming <100> channel orientation CMOS transistors ( | 04-01-2010 |
20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 11-03-2011 |
20120256268 | INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING - Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF. | 10-11-2012 |