Patent application number | Description | Published |
20090008694 | Integrated circuit and corresponding manufacturing method - The present invention provides an integrated circuit including a field effect transistor formed in an active area segment of a semiconductor substrate, the transistor comprising:
| 01-08-2009 |
20090085084 | Integrated Circuit and Methods of Manufacturing the Same - A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned. | 04-02-2009 |
20090085157 | Manufacturing method for an integrated circuit, corresponding intermediate integrated circuit structure and corresponding integrated circuit - The present invention provides a method of manufacturing integrated circuit including a plurality of pillars, comprising the steps of: forming a plurality of first trenches in a first layer comprising a first material, thereby leaving a plurality of fins of the first material between said trenches; forming an infill comprising a second material in said first trenches; forming a plurality of second trenches in said first layer and said infill, the second trenches having sidewalls, walls, wherein first portions of said sidewalls expose the first material, and second portions of said sidewalls expose the second material; and removing either the first or the second material selectively to the respective other material, thereby leaving said pillars of the remaining material. The invention also provides a corresponding intermediate integrated circuit structure. | 04-02-2009 |
20090121315 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE - Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided. | 05-14-2009 |
20090140307 | CONDUCTIVE LINE COMPRISING A CAPPING LAYER - An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound. | 06-04-2009 |
20090294907 | SEMICONDUCTOR COMPONENT WITH MIM CAPACITOR - A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode. | 12-03-2009 |
20090303780 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL - An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line. | 12-10-2009 |
20100027325 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD - An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line. | 02-04-2010 |
20100032635 | ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION - An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench. | 02-11-2010 |
20120279548 | ARRANGEMENT AND CIRCUIT, AND METHOD FOR INTERCONNECTING FLAT SOLAR CELLS - The invention relates to an arrangement and circuit, and to a method for interconnecting flat rigid or flexible solar cells, the photoelectrical active layers thereof being applied to an insulating substrate material. The aim of the invention is provide a novel arrangement and circuit and an associated method for interconnecting flat solar cells, reducing the risk of short circuit and the inactive surface area in the matrix composite of the solar module and selectively allowing simple interconnection, both as a parallel circuit and as a series circuit in production. The solar cells ( | 11-08-2012 |
20140112067 | Apparatus, Storage Device, Switch and Methods, Which Include Microstructures Extending from a Support - An apparatus has a support and a plurality of bendable and conductive microstructures extending from the support. Two adjacent microstructures of the plurality of microstructures define a detectable first state if they are not bent such that end portions thereof, which are distal with respect to the support, do not touch each other, and the two adjacent microstructures of the plurality of microstructures define a detectable second state if they are bent such that the end portions thereof, which are distal with respect to the support, touch each other and are fixed to each other. | 04-24-2014 |
20140134844 | METHOD FOR PROCESSING A DIE - In various embodiments, a method for processing a die is provided. The method may include forming a periodic structure at least one of over and in a carrier, the periodic structure including a plurality of structure elements; depositing masking material over the periodic structure; partially removing masking material to expose at least one structure element but not all of the structure elements; and removing the exposed at least one structure element. | 05-15-2014 |
20140197130 | METHOD FOR MANUFACTURING A PLURALITY OF NANOWIRES - A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment. | 07-17-2014 |
20140209904 | INTEGRATED TEST CIRCUIT AND METHOD FOR MANUFACTURING AN INTEGRATED TEST CIRCUIT - An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads. | 07-31-2014 |
20140233200 | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit may include forming an electronic circuit in or above a carrier; forming at least one metallization layer structure configured to electrically connect the electronic circuit; and forming a solid state electrolyte battery at least partially in the at least one metallization layer structure, wherein the solid state electrolyte battery is electrically connected to the electronic circuit. | 08-21-2014 |
20140273445 | METHOD FOR PROCESSING A CARRIER - A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed. | 09-18-2014 |
20150041811 | Power Transistor - A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width. | 02-12-2015 |
20150084157 | ELECTRONIC STRUCTURE, A BATTERY STRUCTURE, AND A METHOD FOR MANUFACTURING AN ELECTRONIC STRUCTURE - According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries. | 03-26-2015 |
20150086809 | INTEGRATED CIRCUIT STRUCTURE AND A BATTERY STRUCTURE - According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier, and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier. | 03-26-2015 |